534 lines
20 KiB
C
534 lines
20 KiB
C
/****************************************************************************
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* boards/arm/lpc54xx/lpcxpresso-lpc54628/include/board.h
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*
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* Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_LPC54XX_LPCXPRESSO_LPC54628_INCLUDE_BOARD_H
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#define __BOARDS_ARM_LPC54XX_LPCXPRESSO_LPC54628_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking ****************************************************************/
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#undef BOARD_180MHz
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#define BOARD_220MHz 1
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/* System PLL
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*
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* Notation:
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* Fin = the input to the PLL.
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* Fout = the output of the PLL.
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* Fref = the PLL reference frequency, the input to the phase frequency
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* detector.
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* N = optional pre-divider value.
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* M = feedback divider value, which represents the multiplier for the
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* PLL.
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* P = optional post-divider value. An additional divide-by-2 is
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* included in the post-divider path.
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*
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* In all variations of normal mode, the following requirements must be met:
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*
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* -275 MHz ≤ Fcco ≤ 550 MHz.
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* 4 kHz ≤ Fin / N ≤ 25 MHz.
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*
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* Normal mode with optional pre-divide. In the equations, use N = 1 when
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* the pre-divider is not used. The extra divide by 2 is in the feedback
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* divider path:
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*
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* Fout = Fcco = 2 x M x Fin / N
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*
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* Normal mode with post-divide and optional pre-divide. In the equations,
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* use N = 1 when the pre-divider is not used:
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*
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* Fout = Fcco / (2 x P) = M x Fin / (N x P)
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*/
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#define BOARD_PLL_SOURCE /* Select source FR0 12MHz */
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#define BOARD_PLL_FIN LPC54_FRO_12MHZ /* PLL input frequency */
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#ifdef BOARD_180MHz
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/* PLL Clock Source: CLKIN
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* Main Clock Source: PLL
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* Fout: 220000000
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*/
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# define BOARD_PLL_CLKSEL SYSCON_SYSPLLCLKSEL_CLKIN
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# define BOARD_PLL_SELI 32 /* Bandwidth select I value */
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# define BOARD_PLL_SELP 16 /* Bandwidth select P value */
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# define BOARD_PLL_SELR 0 /* Bandwidth select R value */
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# define BOARD_PLL_MDEC 8191 /* Encoded M-divider coefficient */
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# define BOARD_PLL_NDEC 770 /* Encoded N-divider coefficient */
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# define BOARD_PLL_PDEC 98 /* Encoded P-divider coefficient */
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# define BOARD_PLL_FOUT 180000000U /* Pll output frequency */
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#else /* BOARD_220MHz */
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/* PLL Clock Source: FRO 12MHz
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* Main Clock Source: PLL
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* Fout: 220000000
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*/
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# define BOARD_PLL_CLKSEL SYSCON_SYSPLLCLKSEL_FFRO
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# define BOARD_PLL_SELI 34 /* Bandwidth select I value */
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# define BOARD_PLL_SELP 31 /* Bandwidth select P value */
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# define BOARD_PLL_SELR 0 /* Bandwidth select R value */
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# define BOARD_PLL_MDEC 13243 /* Encoded M-divider coefficient */
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# define BOARD_PLL_NDEC 1 /* Encoded N-divider coefficient */
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# define BOARD_PLL_PDEC 98 /* Encoded P-divider coefficient */
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# define BOARD_PLL_FOUT 220000000 /* Pll output frequency */
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#endif
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#define BOARD_MAIN_CLK BOARD_PLL_FOUT /* Main clock frequency */
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/* CPU Clock:
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*
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* AHB Clock Divider: 1
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* AHB Clock Frequency: 180,000,000 or 220,000,000
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*/
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#define BOARD_AHBCLKDIV 1 /* (un-decremented) */
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#define BOARD_AHB_FREQUENCY (BOARD_MAIN_CLK / BOARD_AHBCLKDIV)
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#define BOARD_CPU_FREQUENCY BOARD_AHB_FREQUENCY
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/* Fraction Rate Generator (FRG) Clock (Optional Flexcomm0 function clock)
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*
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* To use the fractional divider, the DIV value must be programmed with the
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* fixed value of 256. Then:
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*
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* Ffrg = (Finput) / (1 + (MULT / DIV))
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*
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* Mainclock is used as the FRG clock source. Divider must be such that the
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* FRG output frequency is less than equal to 48MHz
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*
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* MUL = (Finput - Ffrg) * 256) / Ffrg
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*/
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/* Revisit: FRGCLK <= 48MHz cannot be realized with the MainClk source */
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#define BOARD FRGCLK_CLKSEL SYSCON_FRGCLKSEL_MAINCLK
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#define BOARD_FRGCLK_INPUT BOARD_MAIN_CLK /* FRG input frequency */
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#define BOARD_FRGCLK 48000000 /* May not be exact */
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/* SysTick:
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* The SysTick clock may be clocked internally either by the by the system
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* clock (CLKSOURCE==1) or by the SysTick function clock (CLKSOURCE==0).
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* The SysTick Function clock is equal to:
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*
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* Fsystick = Fmainclk / SYSTICKCLKDIV
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*
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* Tips for selecting BOARD_SYSTICKCLKDIV:
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* The resulting SysTick reload value should be as large as possible,
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* but must be less than 2^24:
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*
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* SYSTICKDIV > Fmainclk / CLK_TCK / 2^24
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*
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* The logic in lpc54_timerisr.c will always select the SysTick function
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* clock as the source (CLKSOURCE==0).
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* NOTE: When the system tick clock divider is selected as the clock source,
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* the CPU clock must be at least 2.5 times faster than the divider output.
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*
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* SysTick Divider: (SYSTICKCLKDIV)
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*/
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#ifndef CONFIG_SCHED_TICKLESS
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# if CONFIG_USEC_PER_TICK == 10000
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# define BOARD_SYSTICKCLKDIV 1
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# else
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# error Missing SYSTICK divider
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# endif
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# define BOARD_SYSTICK_CLOCK (BOARD_AHB_FREQUENCY / BOARD_SYSTICKCLKDIV)
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#endif
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/* Flexcomm0: USART0 (REVIST) */
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#define BOARD_FLEXCOMM0_CLKSEL SYSCON_FCLKSEL_FRO12M
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#define BOARD_FLEXCOMM0_FCLK LPC54_FRO_12MHZ
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/* Flexcomm2: I2C2 (REVIST) */
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#define BOARD_FLEXCOMM2_CLKSEL SYSCON_FCLKSEL_FRO12M
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#define BOARD_FLEXCOMM2_FCLK LPC54_FRO_12MHZ
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/* EMC */
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#ifdef BOARD_220MHz
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#define BOARD_EMC_CLKDIV 3 /* EMC Clock = CPU FREQ/3 */
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#else /* if BOARD_180MHz */
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#define BOARD_EMC_CLKDIV 2 /* EMC Clock = CPU FREQ/2 */
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#endif
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#define BOARD_EMC_FREQUENCY (BOARD_CPU_FREQUENCY / BOARD_EMC_CLKDIV)
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/* SD/MMC or SDIO interface */
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/* SD/MMC function clock. The SDMMC source clock (Fsdmmc) is the main clock
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* which may be divided down by the SYSCON module (8-bit divider, functional
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* range, 1-256). The SD clock is obtained by dividing the source clock
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* down once again (8-bit divider with functional range 1 (bypass) then 2-510
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* in steps of 2).
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*
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* Fsdmmc = Fmck / SYSDIV
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* Fsd = Fsdmmc / SDDIV
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*
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* The optimal SYSCON divisor (SYSDIV) is the smallest divisor that will
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* assure that the smallest usable SD frequency (Fmin = 400KHz) can be
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* attained without overflowing the final 8-bit divider (SDDIV). That is:
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*
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* SYSDIV = Fmck / 400,000 / 510
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*
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* Example: BOARD_MAIN_CLK=220MHz, CLKDIV=2, Finput=110MHz.
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*
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* REVISIT: We could get getter timing resolution if we were to reset the
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* optimal SYSCON divider with each frequency change. For example, at 220
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* MHz, we could set he divider to 1 for all operational frequencies.
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*/
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#define BOARD_SDMMC_CEIL(a,b) (((a) + (b) - 1) / (b))
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#define BOARD_SDMMC_CLKSRC SYSCON_SDIOCLKSEL_MAINCLK
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#define BOARD_SDMMC_CLKDIV BOARD_SDMMC_CEIL(BOARD_MAIN_CLK, 400000 * 510)
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#define BOARD_SDMMC_FREQUENCY (BOARD_MAIN_CLK / BOARD_SDMMC_CLKDIV)
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/* Mode-dependent function clock division
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*
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* Example: BOARD_SDMMC_FREQUENCY=110MHz
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* BOARD_CLKDIV_INIT=276[275], Fsdmmc=399KHz (400KHz max)
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* BOARD_CLKDIV_MMCXFR=6, Fsdmmc=18Mhz (20MHz max)
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* BOARD_CLKDIV_SDWIDEXFR=6[5], Fsdmmc=18MHz (25MHz max)
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* BOARD_CLKDIV_SDXFR=6[5], Fsdmmc=18MHz (25MHz max)
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*
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* NOTE: Clock division is 2*n. For example, value of 0 means divide by
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* 2 * 0 = 0 (no division, bypass), value of 1 means divide by 2 * 1 = 2,
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* value of 255 means divide by 2 * 255 = 510, and so on.
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*
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* SD/MMC logic will write the value ((clkdiv + 1) >> 1) as the divisor.
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* So an odd value calculated below will be moved up to next higher divider
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* value. So the value 3 will cause 2 to be written as the divider value
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* and the effective divider will be 4.
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*/
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#define BOARD_CLKDIV_INIT BOARD_SDMMC_CEIL(BOARD_SDMMC_FREQUENCY, 400000)
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#define BOARD_CLKDIV_MMCXFR BOARD_SDMMC_CEIL(BOARD_SDMMC_FREQUENCY, 20000000)
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#define BOARD_CLKDIV_SDWIDEXFR BOARD_SDMMC_CEIL(BOARD_SDMMC_FREQUENCY, 25000000)
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#define BOARD_CLKDIV_SDXFR BOARD_SDMMC_CEIL(BOARD_SDMMC_FREQUENCY, 25000000)
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/* LED definitions *********************************************************/
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/* The LPCXpress-LPC54628 has three user LEDs: D9, D11, and D12. These
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* LEDs are for application use. They are illuminated when the driving
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* signal from the LPC546xx is low. The LEDs are driven by ports P2-2 (D9),
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* P3-3 (D11) and P3-14 (D12).
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_D9 0
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#define BOARD_D11 1
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#ifndef CONFIG_ARCH_LEDS
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# define BOARD_D12 2
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# define BOARD_NLEDS 3
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#else
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# define BOARD_NLEDS 2
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#endif
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/* LED bits for use with board_userled_all() */
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#define BOARD_D9_BIT (1 << BOARD_D9)
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#define BOARD_D11_BIT (1 << BOARD_D11)
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#ifndef CONFIG_ARCH_LEDS
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# define BOARD_D12_BIT (1 << BOARD_D12)
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#endif
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/* These LEDs are not used by the NuttX port unless CONFIG_ARCH_LEDS is
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* defined. In that case, the usage by the board port is defined in
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* include/board.h and src/lpc54_autoleds.c. The LEDs are used to encode
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* OS-related events as follows:
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*/
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/* D9 D11 D12 */
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#define LED_STARTED 0 /* OFF OFF OFF */
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#define LED_HEAPALLOCATE 1 /* ON OFF OFF */
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#define LED_IRQSENABLED 2 /* OFF ON OFF */
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#define LED_STACKCREATED 3 /* OFF OFF OFF */
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#define LED_INIRQ 4 /* NC NC ON (momentary) */
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#define LED_SIGNAL 4 /* NC NC ON (momentary) */
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#define LED_ASSERTION 4 /* NC NC ON (momentary) */
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#define LED_PANIC 4 /* NC NC ON (2Hz flashing) */
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#undef LED_IDLE /* Sleep mode indication not supported */
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/* After booting, LEDs D9 and D11 are available for use by the user. If the
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* system booted properly, D9 and D11 should be OFF and D12 should be glowing
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* to indicate that interrupts are occurring. If D12 is flash at 2Hz, then
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* the system has crashed.
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*/
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/* Button definitions *******************************************************/
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/* The LPCXpresso has four switches:
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*
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* SW2 ISP2 P0.6
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* SW3 ISP1 P0.5
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* SW4 ISP0 P0.4
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* SW5 User Button P1.1
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*
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* In all cased, the signal is low when the button is pressed.
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*
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* SW2, SW3, SW4 can be used to force the LPC546xx in to ISP boot modes.
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* After boot these buttons could be used as user buttons. However, they are
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* not available when the on-board SRDRAM is used because P0.4, P0.5, and
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* P0.6 are also used as EMC_D2, EMC_D3, and EMC_D4, respectively.
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*
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* So SW5 is really the only button that that is generally available for
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* software usage.
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*/
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#define BUTTON_USER 0
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#define NUM_BUTTONS 1
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#define BUTTON_USER_BIT (1 << BUTTON_USER)
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/* Pin Disambiguation *******************************************************/
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/* Flexcomm0/USART0
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*
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* USART0 connects to the serial bridge on LPC4322JET100 and is typically used
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* for the serial console.
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*
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* BRIDGE_UART_RXD -> P0_29-ISP_FC0_RXD -> P0.29 GPIO_FC0_RXD_SDA_MOSI_2
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* BRIDGE_UART_TXD <- P0_30-ISP_FC0_TXD <- P0.30 GPIO_FC0_TXD_SCL_MISO_2
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*/
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#define GPIO_USART0_RXD (GPIO_FC0_RXD_SDA_MOSI_2 | GPIO_FILTER_OFF)
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#define GPIO_USART0_TXD (GPIO_FC0_TXD_SCL_MISO_2 | GPIO_FILTER_OFF)
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/* An alternative for the serial console is a Arduino Uno compatible serial
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* shield:
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*
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* Arduino Uno J13 Board Signal
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* ----------- ------ ----------------
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* D0 RX Pin 15 P3_26-FC4_RXD
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* D1 TX Pin 13 P3_27-FC4_TXD
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*/
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#define GPIO_USART4_RXD (GPIO_FC4_RXD_SDA_MOSI_2 | GPIO_FILTER_OFF)
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#define GPIO_USART4_TXD (GPIO_FC4_TXD_SCL_MISO_2 | GPIO_FILTER_OFF)
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/* Flexcomm2/I2C
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*
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* For I2C:
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* Type A & D pins need:
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* GPIO_OPENDRAIN + GPIO_FILTER_OFF
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* Type I pins need for Standard mode I2C need:
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* GPIO_FILTER_OFF + GPIO_I2C_FILTER_ON + GPIO_I2CDRIVE_LOW
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* Type I pins need for fast speed I2C need:
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* GPIO_FILTER_OFF + GPIO_I2C_FILTER_ON or OFF +
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* GPIO_I2CDRIVE_LOW or HIGH
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* Type I pins need for high speed I2C need:
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* GPIO_FILTER_OFF + GPIO_I2C_FILTER_OFF + GPIO_I2CDRIVE_HIGH
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*
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* There are several on-board devices using I2C2:
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*
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* Codec I2C address: 0x1a
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* Accel I2C address: 0x1d
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* Touch panel I2C address: 0x38
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*
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* In addition, these same I2C2 pins are brought out through D14 and D15 of
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* the Arduino Uno connector.
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*/
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#if defined(CONFIG_LPC54_I2C_FAST)
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# define _I2CFILTER GPIO_I2C_FILTER_OFF
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# define _I2CDRIVE GPIO_I2CDRIVE_HIGH
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#elif defined(CONFIG_LPC54_I2C_HIGH)
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# define _I2CFILTER GPIO_I2C_FILTER_OFF
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# define _I2CDRIVE GPIO_I2CDRIVE_HIGH
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#else
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# define _I2CFILTER GPIO_I2C_FILTER_ON
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# define _I2CDRIVE GPIO_I2CDRIVE_LOW
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#endif
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#define GPIO_I2C2_SCL (GPIO_FC2_RTS_SCL_SSEL1_2 | \
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GPIO_FILTER_OFF | _I2CFILTER | \
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_I2CDRIVE)
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#define GPIO_I2C2_SDA (GPIO_FC2_CTS_SDA_SSEL0_2 | \
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GPIO_FILTER_OFF | _I2CFILTER | \
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_I2CDRIVE)
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/* Flexcomm2/SPI
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*
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* There are no SPI devices on board the LPCXpresso-LPC54628. SPI is
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* available on the Arduino Uno compatible connector, however:
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*
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* Arduino Uno J9 Board Signal Pin Type
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* ----------- ------ ---------------- ---------
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* D10 SSEL Pin 15 P3_20-FC9_SCK Type D
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* D11 MOSI Pin 13 P3_21-FC9_MOSI Type A
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* D12 MISO Pin 11 P3_22-FC9_MISO Type A
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* D13 SCK Pin 9 P3_30-FC9_SSELn0 Type D
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*
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* For SPI:
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* Type A & D pins need:
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* GPIO_PUSHPULL (on outputs) + GPIO_SLEW_STANDARD (Type D) +
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* GPIO_FILTER_OFF
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* GPIO_SLEW_FAST is optional for high data rates (Type D).
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* Type I need:
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* GPIO_I2C_FILTER_OFF + GPIO_I2CDRIVE_LOW + GPIO_FILTER_OFF +
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* GPIO_I2CSLEW_GPIO
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*/
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#define GPIO_FC9_RXD_SDA_MOSI (GPIO_FC9_RXD_SDA_MOSI_1 | \
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GPIO_PUSHPULL | GPIO_FILTER_OFF)
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#define GPIO_FC9_TXD_SCL_MISO (GPIO_FC9_TXD_SCL_MISO_1 | \
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GPIO_FILTER_OFF)
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#define GPIO_FC9_SCK (GPIO_FC9_SCK_1 | GPIO_PUSHPULL | \
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GPIO_SLEW_STANDARD | GPIO_FILTER_OFF)
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/* SD/MMC
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*
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* P2_10-SD_CDn
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* P2_6-SD_D0
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* P2_7-SD_D1
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* P2_8-SD_D2
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* P2_9-SD_D3
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* P2_3-SD_CLK
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* P2_4-SD_CMD
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* P2_5-SD_POW_EN
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* P3_15-SD_WPn
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*/
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#define GPIO_SD_CARD_DET_N GPIO_SD_CARD_DET_N_2 /* P2.10 */
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#define GPIO_SD_D0 GPIO_SD_D0_3 /* P2.6 */
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#define GPIO_SD_D1 GPIO_SD_D1_3 /* P2.7 */
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#define GPIO_SD_D2 GPIO_SD_D2_3 /* P2.8 */
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#define GPIO_SD_D3 GPIO_SD_D3_3 /* P2.9 */
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#define GPIO_SD_CLK GPIO_SD_CLK_3 /* P2.3 */
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#define GPIO_SD_CMD GPIO_SD_CMD_3 /* P2.4 */
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#define GPIO_SD_POW_EN GPIO_SD_POW_EN_2 /* P2.5 */
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#define GPIO_SD_WR_PRT GPIO_SD_WR_PRT_2 /* P2.15 */
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/* REVISIT: Due to chip errata, Rev. 1.7, Issue 3.7, DAT4-7 must also be
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* configured. Otherwise the SD interface will not work.
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*/
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#define GPIO_SD_D4 (GPIO_SD_D4_3 | GPIO_PULLUP) /* P4.29 */
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#define GPIO_SD_D5 (GPIO_SD_D5_3 | GPIO_PULLUP) /* P4.30 */
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#define GPIO_SD_D6 (GPIO_SD_D6_3 | GPIO_PULLUP) /* P4.31 */
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#define GPIO_SD_D7 (GPIO_SD_D7_3 | GPIO_PULLUP) /* P5.0 */
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/* LCD
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*
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* There are no alternatives for LCD pins except for the VD0-VD3 pins.
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* VD0-VD2 are not used in this hardware configuration. VD3 is on
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* P2.21.
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*/
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#define GPIO_LCD_VD3 GPIO_LCD_VD3_1
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/* Ethernet Clock
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*
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* The Lpcxpresso-LPC546258 uses a LAN8720A PHY in RMII mode. Clocking is
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* provided via a 25MHz crystal (Y1). CLKOUT on P3.12 is an option if JS4
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* is reversed.
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*/
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#define BOARD_PHY_CLOCK 25000000 /* 25MHz crystal */
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/* Ethernet RMII mode pins:
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*
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* P4_16-ENET_MDIO Ethernet MIIM data input and output
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* P4_15-ENET_MDC Ethernet MIIM clock
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*
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* P4_11-ENET_RXD0 Ethernet receive data 0-1
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* P4_12-ENET_RXD1
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* P4_8-ENET_TXD0 Ethernet transmit data 0-1
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* P0_17-ENET_TXD1
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* P4_10-ENET_CRS_DV Ethernet receive data valid
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* P4_13-ENET_TX_EN Ethernet transmit data enable
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*
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* P4_14-ENET_RX_CLK REF_CLK, Reference clock
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* P2_26-ENET_PHY_RSTn nRST (Controlled by board logic)
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*
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* NOTE: You must set JP11 and JP12 to close 1-2 to enable Ethernet
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* port functionality. Some pins are shared with USB0 overcurrent
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* feature.
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*/
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#define GPIO_ENET_MDIO GPIO_ENET_MDIO_2 /* P4.16 */
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#define GPIO_ENET_MDC GPIO_ENET_MDC_2 /* P4.15 */
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#define GPIO_ENET_RXD0 GPIO_ENET_RXD0_2 /* P4.11 */
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#define GPIO_ENET_RXD1 GPIO_ENET_RXD1_2 /* P4.12 */
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#define GPIO_ENET_TXD0 GPIO_ENET_TXD0_3 /* P4.8 */
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#define GPIO_ENET_TXD1 GPIO_ENET_TXD1_4 /* P0.17 */
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#define GPIO_ENET_RX_DV GPIO_ENET_RX_DV_2 /* P4.10 */
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#define GPIO_ENET_TX_EN GPIO_ENET_TX_EN_2 /* P4.13 */
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#define GPIO_ENET_REF_CLK GPIO_ENET_RX_CLK_2 /* P4.14 */
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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|
/****************************************************************************
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|
* Public Data
|
|
****************************************************************************/
|
|
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|
#undef EXTERN
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|
#if defined(__cplusplus)
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|
#define EXTERN extern "C"
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|
extern "C"
|
|
{
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|
#else
|
|
#define EXTERN extern
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Public Function Prototypes
|
|
****************************************************************************/
|
|
|
|
#undef EXTERN
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#if defined(__cplusplus)
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}
|
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#endif
|
|
|
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#endif /* __ASSEMBLY__ */
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#endif /* __BOARDS_ARM_LPC54XX_LPCXPRESSO_LPC54628_INCLUDE_BOARD_H */
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