ae22eb224a
GPIO and UART seem similar across STMicro product matrix, so renamed files accordingly. RCC is cloned just in case, while conflicting differences there seem to be very minor.
255 lines
14 KiB
C
255 lines
14 KiB
C
/************************************************************************************
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* arch/arm/include/stm32l4/chip.h
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*
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* Copyright (C) 2016 Sebastien Lorquet. All rights reserved.
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* Author: Sebastien Lorquet <sebastien@lorquet.fr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_STM32L4_CHIP_H
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#define __ARCH_ARM_INCLUDE_STM32L4_CHIP_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* STM32L476, STM32L486, STM32L496, STM32L4A6
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*
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* Differences between family members:
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* - L486 has AES
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* - L496, L4A6 has 320 Kib SRAM, 2xCAN and CameraIF. Most (all?) of these have I2C4.
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* - L4A6 has AES and HASH
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*
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* ----------- ---------------- ----- ------ ------ ---- ---- -----
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* PART PACKAGE GPIOs LCD Tamper FSMC CapS AdcCh
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* ----------- ---------------- ----- ------ ------ ---- ---- -----
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* STM32L4x6Jx WLCSP72L 57 8x28 2 No 12 16
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* STM32L476Mx WLCSP81L 65 ? ? ? ? ?
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* STM32L4x6Qx UFBGA132L 109 8x40 3 Yes 24 16
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* STM32L4x6Rx LQFP64 51 8x28 2 No 12 16
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* STM32L4x6Vx LQFP100 82 8x40 3 Yes 21 16
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* STM32L4x6Zx LQFP144 114 8x40 3 Yes 24 24
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* STM32L4x6Ax UFBGA169 132 8x40 3 Yes 24 24
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* ----------- ---------------- ----- ------ ------ ---- ---- -----
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*
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* Parts STM32L4x6xC have 256Kb of FLASH
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* Parts STM32L4x6xE have 512Kb of FLASH
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* Parts STM32L4x6xG have 1024Kb of FLASH
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*
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* The correct FLASH size must be set with a CONFIG_STM32L4_FLASH_CONFIG_*
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* selection.
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*/
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#if defined(CONFIG_STM32L4_STM32L496XX)
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# define STM32L4_SRAM1_SIZE (256*1024) /* 256Kb SRAM1 on AHB bus Matrix */
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# define STM32L4_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */
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#elif defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX)
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# define STM32L4_SRAM1_SIZE (96*1024) /* 96Kb SRAM1 on AHB bus Matrix */
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# define STM32L4_SRAM2_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix */
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#elif defined(CONFIG_STM32L4_STM32L451XX) || defined(CONFIG_STM32L4_STM32L452XX) || \
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defined(CONFIG_STM32L4_STM32L462XX)
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# define STM32L4_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix */
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# define STM32L4_SRAM2_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix */
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#elif defined(CONFIG_STM32L4_STM32L432XX)
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# define STM32L4_SRAM1_SIZE (48*1024) /* 48Kb SRAM1 on AHB bus Matrix */
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# define STM32L4_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
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#else
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# error "Unsupported STM32L4 chip"
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#endif
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#if defined(CONFIG_STM32L4_STM32L4X6)
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# define STM32L4_NFSMC 1 /* Have FSMC memory controller */
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# define STM32L4_NATIM 2 /* Two advanced timers TIM1 and 8 */
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# define STM32L4_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
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# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */
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# define STM32L4_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */
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# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
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# define STM32L4_NRNG 1 /* Random number generator (RNG) */
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# define STM32L4_NUART 2 /* UART 4-5 */
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# define STM32L4_NUSART 3 /* USART 1-3 */
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# define STM32L4_NLPUART 1 /* LPUART 1 */
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# define STM32L4_NSPI 3 /* SPI1-3 */
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#if defined(CONFIG_STM32L4_STM32L496XX)
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# define STM32L4_NI2C 4 /* I2C1-4 */
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#else
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# define STM32L4_NI2C 3 /* I2C1-3 */
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#endif
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# define STM32L4_NUSBOTGFS 1 /* USB OTG FS */
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# define STM32L4_NUSBFS 0 /* No USB FS */
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#if defined(CONFIG_STM32L4_STM32L496XX)
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# define STM32L4_NCAN 2 /* CAN1-2 */
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#else
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# define STM32L4_NCAN 1 /* CAN1 */
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#endif
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# define STM32L4_NSAI 2 /* SAI1-2 */
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# define STM32L4_NSDMMC 1 /* SDMMC interface */
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# define STM32L4_NDMA 2 /* DMA1-2 */
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#if defined(CONFIG_STM32L4_STM32L496XX)
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# define STM32L4_NPORTS 9 /* 9 GPIO ports, GPIOA-I */
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#else
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# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
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#endif
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# define STM32L4_NADC 3 /* 12-bit ADC1-3, upto 24 channels */
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# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32L4_NCRC 1 /* CRC */
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# define STM32L4_NCOMP 2 /* Comparators */
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# define STM32L4_NOPAMP 2 /* Operational Amplifiers */
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#endif /* CONFIG_STM32L4_STM32L4X6 */
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#if defined(CONFIG_STM32L4_STM32L451XX) || defined(CONFIG_STM32L4_STM32L452XX) || \
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defined(CONFIG_STM32L4_STM32L462XX)
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# define STM32L4_NFSMC 0 /* No FSMC memory controller */
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# define STM32L4_NATIM 1 /* One advanced timer TIM1 */
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# define STM32L4_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */
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# define STM32L4_NGTIM16 3 /* 16-bit general timers TIM3, TIM15-16 with DMA */
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# define STM32L4_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
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# define STM32L4_NBTIM 1 /* One basic timer, TIM6 */
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# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
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# define STM32L4_NRNG 1 /* Random number generator (RNG) */
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# define STM32L4_NUART 1 /* UART 4 */
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# define STM32L4_NUSART 3 /* USART 1-3 */
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# define STM32L4_NLPUART 1 /* LPUART 1 */
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# define STM32L4_NSPI 3 /* SPI1-3 */
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# define STM32L4_NI2C 4 /* I2C1-4 */
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# define STM32L4_NUSBOTGFS 0 /* No USB OTG FS */
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#if defined(CONFIG_STM32L4_STM32L451XX)
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# define STM32L4_NUSBFS 0 /* No USB FS */
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#else
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# define STM32L4_NUSBFS 1 /* USB FS */
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#endif
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# define STM32L4_NCAN 1 /* CAN1 */
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# define STM32L4_NSAI 1 /* SAI1 */
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#if defined(CONFIG_STM32L4_HAVE_SDMMC1)
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# define STM32L4_NSDMMC 1 /* SDMMC interface */
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#else
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# define STM32L4_NSDMMC 0 /* No SDMMC interface */
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#endif
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# define STM32L4_NDMA 2 /* DMA1-2 */
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# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
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# define STM32L4_NADC 1 /* 12-bit ADC1, 16 channels (10 in CE,CV) */
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# define STM32L4_NDAC 1 /* 12-bit DAC1 */
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# define STM32L4_NCRC 1 /* CRC */
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# define STM32L4_NCOMP 2 /* Comparators */
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# define STM32L4_NOPAMP 1 /* Operational Amplifiers */
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#endif /* CONFIG_STM32L4_STM32L451XX */
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#if defined(CONFIG_STM32L4_STM32L432XX)
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# define STM32L4_NFSMC 0 /* No FSMC memory controller */
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# define STM32L4_NATIM 1 /* One advanced timer TIM1 */
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# define STM32L4_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */
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# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */
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# define STM32L4_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
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# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */
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# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
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# define STM32L4_NRNG 1 /* Random number generator (RNG) */
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# define STM32L4_NUART 0 /* No UART */
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# define STM32L4_NUSART 2 /* USART 1-2 */
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# define STM32L4_NLPUART 1 /* LPUART 1 */
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# define STM32L4_NSPI 2 /* SPI1, SPI3 */
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# define STM32L4_NI2C 2 /* I2C1, I2C3 */
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# define STM32L4_NUSBOTGFS 0 /* No USB OTG FS */
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# define STM32L4_NUSBFS 1 /* USB FS */
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# define STM32L4_NCAN 1 /* CAN1 */
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# define STM32L4_NSAI 1 /* SAI1 */
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# define STM32L4_NSDMMC 0 /* No SDMMC interface */
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# define STM32L4_NDMA 2 /* DMA1-2 */
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# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */
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# define STM32L4_NADC 1 /* 12-bit ADC1, 10 channels */
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# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */
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# define STM32L4_NCRC 1 /* CRC */
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# define STM32L4_NCOMP 2 /* Comparators */
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# define STM32L4_NOPAMP 1 /* Operational Amplifiers */
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#endif /* CONFIG_STM32L4_STM32L432XX */
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/* NVIC priority levels *************************************************************/
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/* 16 Programmable interrupt levels */
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#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
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/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled
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* by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most
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* interrupts will not have execution priority. SVCall must have execution
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* priority in all cases.
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*
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* In the normal cases, interrupts are not nest-able and all interrupts run
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* at an execution priority between NVIC_SYSH_PRIORITY_MIN and
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* NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall).
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*
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* If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special
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* high priority interrupts are supported. These are not "nested" in the
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* normal sense of the word. These high priority interrupts can interrupt
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* normal processing but execute outside of OS (although they can "get back
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* into the game" via a PendSV interrupt).
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*
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* In the normal course of things, interrupts must occasionally be disabled
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* using the irqsave() inline function to prevent contention in use of
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* resources that may be shared between interrupt level and non-interrupt
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* level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT,
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* do we disable all interrupts (except SVCall), or do we only disable the
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* "normal" interrupts. Since the high priority interrupts cannot interact
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* with the OS, you may want to permit the high priority interrupts even if
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* interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be
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* used to select either behavior:
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*
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* ----------------------------+--------------+----------------------------
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* CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES
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* ----------------------------+--------------+--------------+-------------
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* CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO
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* ----------------------------+--------------+--------------+-------------
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* | | | SVCall
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* | SVCall | SVCall | HIGH
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* Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL
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* | | MAXNORMAL |
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* ----------------------------+--------------+--------------+-------------
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*/
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#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL)
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# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP)
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# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
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# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY
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# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
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#else
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# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
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# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX
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# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY
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# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
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#endif
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#endif /* __ARCH_ARM_INCLUDE_STM32L4_CHIP_H */
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