cf431c9397
stm3240g-eval: Add a configuration for testing the FB character driver at drivers/video/fb.c using the LCD frame driver front end at drivers/lcd/lcd_framebuffer.c. Appears to be fully functional.
stm3240g-eval: Replace the old-style stm32_appinit.c with tne new one from the STM32F4-Discovery
stm3240g-eval: Rename stm32_appinit.c to stm32_bringup.c to better match other architectures
518 lines
18 KiB
C
518 lines
18 KiB
C
/************************************************************************************
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* configs/stm3240g-eval/include/board.h
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* include/arch/board/board.h
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*
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* Copyright (C) 2011-2012, 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_BOARD_BOARD_H
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#define __ARCH_BOARD_BOARD_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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/* Logic in arch/arm/src and configs/ may need to include these file prior to
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* including board.h: stm32_rcc.h, stm32_sdio.h, stm32.h. They cannot be included
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* here because board.h is used in other contexts where the STM32 internal header
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* files are not available.
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*/
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Clocking *************************************************************************/
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/* Four clock sources are available on STM3240G-EVAL evaluation board for
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* STM32F407IGH6 and RTC embedded:
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*
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* X1, 25 MHz crystal for Ethernet PHY with socket. It can be removed when clock is
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* provided by MCO pin of the MCU
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* X2, 26 MHz crystal for USB OTG HS PHY
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* X3, 32 kHz crystal for embedded RTC
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* X4, 25 MHz crystal with socket for STM32F407IGH6 microcontroller (It can be removed
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* from socket when internal RC clock is used.)
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*
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* This is the "standard" configuration as set up by arch/arm/src/stm32f40xx_rcc.c:
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* System Clock source : PLL (HSE)
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* SYSCLK(Hz) : 168000000 Determined by PLL configuration
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* HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE)
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* AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE)
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* APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1)
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* APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2)
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* HSE Frequency(Hz) : 25000000 (STM32_BOARD_XTAL)
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* PLLM : 25 (STM32_PLLCFG_PLLM)
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* PLLN : 336 (STM32_PLLCFG_PLLN)
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* PLLP : 2 (STM32_PLLCFG_PLLP)
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* PLLQ : 7 (STM32_PLLCFG_PLLQ)
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* Main regulator output voltage : Scale1 mode Needed for high speed SYSCLK
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* Flash Latency(WS) : 5
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* Prefetch Buffer : OFF
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* Instruction cache : ON
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* Data cache : ON
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* Require 48MHz for USB OTG FS, : Enabled
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* SDIO and RNG clock
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*/
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/* HSI - 16 MHz RC factory-trimmed
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* LSI - 32 KHz RC
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* HSE - On-board crystal frequency is 25MHz
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* LSE - 32.768 kHz
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*/
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#define STM32_BOARD_XTAL 25000000ul
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#define STM32_HSI_FREQUENCY 16000000ul
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#define STM32_LSI_FREQUENCY 32000
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_LSE_FREQUENCY 32768
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/* Main PLL Configuration.
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*
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* PLL source is HSE
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* PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
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* = (25,000,000 / 25) * 336
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* = 336,000,000
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* SYSCLK = PLL_VCO / PLLP
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* = 336,000,000 / 2 = 168,000,000
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* USB OTG FS, SDIO and RNG Clock
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* = PLL_VCO / PLLQ
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* = 48,000,000
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*/
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25)
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336)
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
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#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7)
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#define STM32_SYSCLK_FREQUENCY 168000000ul
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/* AHB clock (HCLK) is SYSCLK (168MHz) */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
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/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
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/* Timers driven from APB1 will be twice PCLK1 */
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
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/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* Timers driven from APB2 will be twice PCLK2 */
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#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY)
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
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* otherwise frequency is 2xAPBx.
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* Note: TIM1,8 are on APB2, others on APB1
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*/
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#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY
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/* SDIO dividers. Note that slower clocking is required when DMA is disabled
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* in order to avoid RX overrun/TX underrun errors due to delayed responses
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* to service FIFOs in interrupt driven mode. These values have not been
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* tuned!!!
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*
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* SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz
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*/
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#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT)
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/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz
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* DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz
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*/
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#ifdef CONFIG_SDIO_DMA
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# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
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#else
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# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
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#endif
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/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz
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* DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz
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*/
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#ifdef CONFIG_SDIO_DMA
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# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
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#else
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# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
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#endif
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/* Ethernet *************************************************************************/
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/* We need to provide clocking to the MII PHY via MCO1 (PA8) */
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#if defined(CONFIG_NET) && defined(CONFIG_STM32_ETHMAC)
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# if !defined(CONFIG_STM32_MII)
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# warning "CONFIG_STM32_MII required for Ethernet"
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# elif !defined(CONFIG_STM32_MII_MCO1)
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# warning "CONFIG_STM32_MII_MCO1 required for Ethernet MII"
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# else
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/* Output HSE clock (25MHz) on MCO1 pin (PA8) to clock the PHY */
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# define BOARD_CFGR_MC01_SOURCE RCC_CFGR_MCO1_HSE
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# define BOARD_CFGR_MC01_DIVIDER RCC_CFGR_MCO1PRE_NONE
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# endif
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#endif
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/* LED definitions ******************************************************************/
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/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any
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* way. The following definitions are used to access individual LEDs.
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_LED1 0
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#define BOARD_LED2 1
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#define BOARD_LED3 2
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#define BOARD_LED4 3
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#define BOARD_NLEDS 4
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/* LED bits for use with board_userled_all() */
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#define BOARD_LED1_BIT (1 << BOARD_LED1)
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#define BOARD_LED2_BIT (1 << BOARD_LED2)
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#define BOARD_LED3_BIT (1 << BOARD_LED3)
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#define BOARD_LED4_BIT (1 << BOARD_LED4)
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/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on board the
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* STM3240G-EVAL. The following definitions describe how NuttX controls the LEDs:
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*/
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#define LED_STARTED 0 /* LED1 */
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#define LED_HEAPALLOCATE 1 /* LED2 */
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#define LED_IRQSENABLED 2 /* LED1 + LED2 */
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#define LED_STACKCREATED 3 /* LED3 */
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#define LED_INIRQ 4 /* LED1 + LED3 */
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#define LED_SIGNAL 5 /* LED2 + LED3 */
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#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */
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#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */
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/* Button definitions ***************************************************************/
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/* The STM3240G-EVAL supports three buttons: */
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#define BUTTON_WAKEUP 0
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#define BUTTON_TAMPER 1
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#define BUTTON_USER 2
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#define NUM_BUTTONS 3
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#define BUTTON_WAKEUP_BIT (1 << BUTTON_WAKEUP)
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#define BUTTON_TAMPER_BIT (1 << BUTTON_TAMPER)
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#define BUTTON_USER_BIT (1 << BUTTON_USER)
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/* SRAM definitions *****************************************************************/
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/* The 16 Mbit SRAM is connected to the STM32F407IGH6 FSMC bus which shares the same
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* I/Os with the CAN1 bus. Jumper settings:
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*
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* JP1: Connect PE4 to SRAM as A20
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* JP2: onnect PE3 to SRAM as A19
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*
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* JP3 and JP10 must not be fitted for SRAM and LCD application. JP3 and JP10
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* select CAN1 or CAN2 if fitted; neither if not fitted.
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*/
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#if defined(CONFIG_STM32_FSMC) && defined(CONFIG_STM32_FSMC_SRAM)
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# if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2)
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# error "The STM3240G-EVAL cannot support both CAN and FSMC SRAM"
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# endif
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#endif
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/* This is the Bank1 SRAM2 address: */
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#define BOARD_SRAM_BASE 0x64000000
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#define BOARD_SRAM_SIZE (2*1024*1024)
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/* Alternate function pin selections ************************************************/
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/* UART3:
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*
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* - PC11 is MicroSDCard_D3 & RS232/IrDA_RX (JP22 open)
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* - PC10 is MicroSDCard_D2 & RSS232/IrDA_TX
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*/
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#define GPIO_USART3_RX GPIO_USART3_RX_2
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#define GPIO_USART3_TX GPIO_USART3_TX_2
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/* Ethernet:
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*
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* - PA2 is ETH_MDIO
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* - PC1 is ETH_MDC
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* - PB5 is ETH_PPS_OUT
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* - PH2 is ETH_MII_CRS
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* - PH3 is ETH_MII_COL
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* - PI10 is ETH_MII_RX_ER
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* - PH6 is ETH_MII_RXD2
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* - PH7 is ETH_MII_RXD3
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* - PC3 is ETH_MII_TX_CLK
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* - PC2 is ETH_MII_TXD2
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* - PB8 is ETH_MII_TXD3
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* - PA1 is ETH_MII_RX_CLK/ETH_RMII_REF_CLK
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* - PA7 is ETH_MII_RX_DV/ETH_RMII_CRS_DV
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* - PC4 is ETH_MII_RXD0/ETH_RMII_RXD0
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* - PC5 is ETH_MII_RXD1/ETH_RMII_RXD1
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* - PG11 is ETH_MII_TX_EN/ETH_RMII_TX_EN
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* - PG13 is ETH_MII_TXD0/ETH_RMII_TXD0
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* - PG14 is ETH_MII_TXD1/ETH_RMII_TXD1
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*/
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#define GPIO_ETH_PPS_OUT GPIO_ETH_PPS_OUT_1
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#define GPIO_ETH_MII_CRS GPIO_ETH_MII_CRS_2
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#define GPIO_ETH_MII_COL GPIO_ETH_MII_COL_2
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#define GPIO_ETH_MII_RX_ER GPIO_ETH_MII_RX_ER_2
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#define GPIO_ETH_MII_RXD2 GPIO_ETH_MII_RXD2_2
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#define GPIO_ETH_MII_RXD3 GPIO_ETH_MII_RXD3_2
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#define GPIO_ETH_MII_TXD3 GPIO_ETH_MII_TXD3_1
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#define GPIO_ETH_MII_TX_EN GPIO_ETH_MII_TX_EN_2
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#define GPIO_ETH_MII_TXD0 GPIO_ETH_MII_TXD0_2
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#define GPIO_ETH_MII_TXD1 GPIO_ETH_MII_TXD1_2
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#define GPIO_ETH_RMII_TX_EN GPIO_ETH_RMII_TX_EN_2
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#define GPIO_ETH_RMII_TXD0 GPIO_ETH_RMII_TXD0_2
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#define GPIO_ETH_RMII_TXD1 GPIO_ETH_RMII_TXD1_2
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/* PWM
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*
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* The STM3240G-Eval has no real on-board PWM devices, but the board can be
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* configured to output a pulse train using the following:
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*
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* If FSMC is not used:
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* TIM4 CH2OUT: PD13 FSMC_A18 / MC_TIM4_CH2OUT
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* Daughterboard Extension Connector, CN3, pin 32
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* Motor Control Connector CN15, pin 33 -- not available unless you bridge SB14.
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*
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* TIM1 CH1OUT: PE9 FSMC_D6
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* Daughterboard Extension Connector, CN2, pin 24
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*
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* TIM1_CH2OUT: PE11 FSMC_D8
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* Daughterboard Extension Connector, CN2, pin 26
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*
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* TIM1_CH3OUT: PE13 FSMC_D10
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* Daughterboard Extension Connector, CN2, pin 28
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*
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* TIM1_CH4OUT: PE14 FSMC_D11
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* Daughterboard Extension Connector, CN2, pin 29
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*
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* If OTG FS is not used
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*
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* TIM1_CH3OUT: PA10 OTG_FS_ID
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* Daughterboard Extension Connector, CN3, pin 14
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*
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* TIM1_CH4OUT: PA11 OTG_FS_DM
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* Daughterboard Extension Connector, CN3, pin 11
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*
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* If DMCI is not used
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*
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* TIM8 CH1OUT: PI5 DCMI_VSYNC & MC
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* Daughterboard Extension Connector, CN4, pin 4
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*
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* TIM8_CH2OUT: PI6 DCMI_D6 & MC
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* Daughterboard Extension Connector, CN4, pin 3
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*
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* TIM8_CH3OUT: PI7 DCMI_D7 & MC
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* Daughterboard Extension Connector, CN4, pin 2
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*
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* If SDIO is not used
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*
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* TIM8_CH3OUT: PC8 MicroSDCard_D0 & MC
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* Daughterboard Extension Connector, CN3, pin 18
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*
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* TIM8_CH4OUT: PC9 MicroSDCard_D1 & I2S_CKIN (Need JP16 open)
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* Daughterboard Extension Connector, CN3, pin 17
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*
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* Others
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*
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* TIM8 CH1OUT: PC6 I2S_MCK & Smartcard_IO (JP21 open)
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*/
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#if !defined(CONFIG_STM32_FSMC)
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# define GPIO_TIM4_CH2OUT GPIO_TIM4_CH2OUT_2
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# define GPIO_TIM1_CH1OUT GPIO_TIM1_CH1OUT_2
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# define GPIO_TIM1_CH2OUT GPIO_TIM1_CH2OUT_2
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# define GPIO_TIM1_CH3OUT GPIO_TIM1_CH3OUT_2
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# define GPIO_TIM1_CH4OUT GPIO_TIM1_CH4OUT_2
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#elif !defined(CONFIG_STM32_OTGFS)
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# define GPIO_TIM1_CH3OUT GPIO_TIM1_CH3OUT_1
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# define GPIO_TIM1_CH4OUT GPIO_TIM1_CH4OUT_1
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#endif
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#if !defined(CONFIG_STM32_DCMI)
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# define GPIO_TIM8_CH1OUT GPIO_TIM8_CH1OUT_2
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# define GPIO_TIM8_CH2OUT GPIO_TIM8_CH2OUT_2
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# define GPIO_TIM8_CH3OUT GPIO_TIM8_CH3OUT_2
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#else
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# define GPIO_TIM8_CH1OUT GPIO_TIM8_CH1OUT_1
|
|
# if !defined(CONFIG_STM32_SDIO)
|
|
# define GPIO_TIM8_CH3OUT GPIO_TIM8_CH3OUT_1
|
|
# endif
|
|
#endif
|
|
|
|
#if !defined(CONFIG_STM32_SDIO)
|
|
# define GPIO_TIM8_CH4OUT GPIO_TIM8_CH4OUT_1
|
|
#endif
|
|
|
|
/* CAN
|
|
*
|
|
* Connector 10 (CN10) is DB-9 male connector that can be used with CAN1 or CAN2.
|
|
*
|
|
* JP10 connects CAN1_RX or CAN2_RX to the CAN transceiver
|
|
* JP3 connects CAN1_TX or CAN2_TX to the CAN transceiver
|
|
*
|
|
* CAN signals are then available on CN10 pins:
|
|
*
|
|
* CN10 Pin 7 = CANH
|
|
* CN10 Pin 2 = CANL
|
|
*
|
|
* Mapping to STM32 GPIO pins:
|
|
*
|
|
* PD0 = FSMC_D2 & CAN1_RX
|
|
* PD1 = FSMC_D3 & CAN1_TX
|
|
* PB13 = ULPI_D6 & CAN2_TX
|
|
* PB5 = ULPI_D7 & CAN2_RX
|
|
*/
|
|
|
|
#define GPIO_CAN1_RX GPIO_CAN1_RX_3
|
|
#define GPIO_CAN1_TX GPIO_CAN1_TX_3
|
|
|
|
#define GPIO_CAN2_RX GPIO_CAN2_RX_2
|
|
#define GPIO_CAN2_TX GPIO_CAN2_TX_1
|
|
|
|
/* I2C. Only I2C1 is available on the STM3240G-EVAL. I2C1_SCL and I2C1_SDA are
|
|
* available on the following pins:
|
|
*
|
|
* - PB6 is I2C1_SCL
|
|
* - PB9 is I2C1_SDA
|
|
*/
|
|
|
|
#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1
|
|
#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2
|
|
|
|
/* DMA Channl/Stream Selections *****************************************************/
|
|
/* Stream selections are arbitrary for now but might become important in the future
|
|
* if we set aside more DMA channels/streams.
|
|
*
|
|
* SDIO DMA
|
|
* DMAMAP_SDIO_1 = Channel 4, Stream 3
|
|
* DMAMAP_SDIO_2 = Channel 4, Stream 6
|
|
*/
|
|
|
|
#define DMAMAP_SDIO DMAMAP_SDIO_1
|
|
|
|
/************************************************************************************
|
|
* Public Data
|
|
************************************************************************************/
|
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
#undef EXTERN
|
|
#if defined(__cplusplus)
|
|
#define EXTERN extern "C"
|
|
extern "C"
|
|
{
|
|
#else
|
|
#define EXTERN extern
|
|
#endif
|
|
|
|
/************************************************************************************
|
|
* Public Function Prototypes
|
|
************************************************************************************/
|
|
/************************************************************************************
|
|
* Name: stm32_boardinitialize
|
|
*
|
|
* Description:
|
|
* All STM32 architectures must provide the following entry point. This entry point
|
|
* is called early in the intitialization -- after all memory has been configured
|
|
* and mapped but before any devices have been initialized.
|
|
*
|
|
************************************************************************************/
|
|
|
|
void stm32_boardinitialize(void);
|
|
|
|
/************************************************************************************
|
|
* Name: stm3240g_lcdclear
|
|
*
|
|
* Description:
|
|
* This is a non-standard LCD interface just for the STM3210E-EVAL board. Because
|
|
* of the various rotations, clearing the display in the normal way by writing a
|
|
* sequences of runs that covers the entire display can be very slow. Here the
|
|
* dispaly is cleared by simply setting all GRAM memory to the specified color.
|
|
*
|
|
************************************************************************************/
|
|
|
|
#ifdef CONFIG_STM32_FSMC
|
|
void stm3240g_lcdclear(uint16_t color);
|
|
#endif
|
|
|
|
#undef EXTERN
|
|
#if defined(__cplusplus)
|
|
}
|
|
#endif
|
|
|
|
#endif /* __ASSEMBLY__ */
|
|
#endif /* __ARCH_BOARD_BOARD_H */
|