164 lines
8.2 KiB
C
164 lines
8.2 KiB
C
/************************************************************************************
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* arch/arm/src/lpc2378/lpc23xx_spi.h
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*
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* Copyright (C) 2013 Li Zhuoyi. All rights reserved.
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* Author: Li Zhuoyi <lzyy.cn@gmail.com>
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*
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* Derived arch/arm/src/lpc17xx/lpc17_spi.h
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*
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* Copyright (C) 2010, 2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC2378_LPC23XX_SPI_H
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#define __ARCH_ARM_SRC_LPC2378_LPC23XX_SPI_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* SPI Pin Configuration ************************************************************/
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#define SPI_BASE SPI0_BASE_ADDR
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#define SPI_PCLKSEL_MASK (0x03 << 16)
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#define SPI_PCLKSEL (0x01 << 16)
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#define SPI_PINSEL0_MASK (0x03 << 30) /* P0.15 SCK PINSEL0 */
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#define SPI_PINSEL1_MASK (0x0f << 2) /* P0.17 P0.18 PINSEL1 */
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#define SPI_PINSEL0 (0x03 << 30)
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#define SPI_PINSEL1 (0x0f << 2)
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/* SPI PRegister offsets ************************************************************/
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#define SPI_CR_OFFSET 0x0000 /* Control Register */
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#define SPI_SR_OFFSET 0x0004 /* SPI Status Register */
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#define SPI_DR_OFFSET 0x0008 /* SPI Data Register */
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#define SPI_CCR_OFFSET 0x000c /* SPI Clock Counter Register */
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#define SPI_TCR_OFFSET 0x0010 /* SPI Test Control Register */
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#define SPI_TSR_OFFSET 0x0014 /* SPI Test Status Register */
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#define SPI_INT_OFFSET 0x001c /* SPI Interrupt Register */
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/* SPI Register addresses ***********************************************************/
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#define SPI_CR (SPI_BASE+SPI_CR_OFFSET)
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#define SPI_SR (SPI_BASE+SPI_SR_OFFSET)
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#define SPI_DR (SPI_BASE+SPI_DR_OFFSET)
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#define SPI_CCR (SPI_BASE+SPI_CCR_OFFSET)
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#define TCR_CCR (SPI_BASE+SPI_TCR_OFFSET)
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#define TSR_CCR (SPI_BASE+SPI_TSR_OFFSET)
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#define SPI_INT (SPI_BASE+SPI_INT_OFFSET)
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/* SPI Register bit definitions *****************************************************/
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/* Control Register */
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/* Bits 0-1: Reserved */
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#define SPI_CR_BITENABLE (1 << 2) /* Bit 2: Enable word size selected by BITS */
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#define SPI_CR_CPHA (1 << 3) /* Bit 3: Clock phase control */
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#define SPI_CR_CPOL (1 << 4) /* Bit 4: Clock polarity control */
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#define SPI_CR_MSTR (1 << 5) /* Bit 5: Master mode select */
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#define SPI_CR_LSBF (1 << 6) /* Bit 6: SPI data is transferred LSB first */
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#define SPI_CR_SPIE (1 << 7) /* Bit 7: Serial peripheral interrupt enable */
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#define SPI_CR_BITS_SHIFT (8) /* Bits 8-11: Number of bits per word (BITENABLE==1) */
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#define SPI_CR_BITS_MASK (15 << SPI_CR_BITS_SHIFT)
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# define SPI_CR_BITS_8BITS (8 << SPI_CR_BITS_SHIFT) /* 8 bits per transfer */
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# define SPI_CR_BITS_9BITS (9 << SPI_CR_BITS_SHIFT) /* 9 bits per transfer */
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# define SPI_CR_BITS_10BITS (10 << SPI_CR_BITS_SHIFT) /* 10 bits per transfer */
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# define SPI_CR_BITS_11BITS (11 << SPI_CR_BITS_SHIFT) /* 11 bits per transfer */
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# define SPI_CR_BITS_12BITS (12 << SPI_CR_BITS_SHIFT) /* 12 bits per transfer */
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# define SPI_CR_BITS_13BITS (13 << SPI_CR_BITS_SHIFT) /* 13 bits per transfer */
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# define SPI_CR_BITS_14BITS (14 << SPI_CR_BITS_SHIFT) /* 14 bits per transfer */
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# define SPI_CR_BITS_15BITS (15 << SPI_CR_BITS_SHIFT) /* 15 bits per transfer */
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# define SPI_CR_BITS_16BITS (0 << SPI_CR_BITS_SHIFT) /* 16 bits per transfer */
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/* Bits 12-31: Reserved */
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/* SPI Status Register */
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/* Bits 0-2: Reserved */
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#define SPI_SR_ABRT (1 << 3) /* Bit 3: Slave abort */
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#define SPI_SR_MODF (1 << 4) /* Bit 4: Mode fault */
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#define SPI_SR_ROVR (1 << 5) /* Bit 5: Read overrun */
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#define SPI_SR_WCOL (1 << 6) /* Bit 6: Write collision */
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#define SPI_SR_SPIF (1 << 7) /* Bit 7: SPI transfer complete */
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/* Bits 8-31: Reserved */
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/* SPI Data Register */
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#define SPI_DR_MASK (0xff) /* Bits 0-15: SPI Bi-directional data port */
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#define SPI_DR_MASKWIDE (0xffff) /* Bits 0-15: If SPI_CR_BITENABLE != 0 */
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/* Bits 8-31: Reserved */
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/* SPI Clock Counter Register */
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#define SPI_CCR_MASK (0xff) /* Bits 0-7: SPI Clock counter setting */
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/* Bits 8-31: Reserved */
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/* SPI Test Control Register */
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/* Bit 0: Reserved */
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#define SPI_TCR_TEST_SHIFT (1) /* Bits 1-7: SPI test mode */
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#define SPI_TCR_TEST_MASK (0x7f << SPI_TCR_TEST_SHIFT)
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/* Bits 8-31: Reserved */
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/* SPI Test Status Register */
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/* Bits 0-2: Reserved */
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#define SPI_TSR_ABRT (1 << 3) /* Bit 3: Slave abort */
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#define SPI_TSR_MODF (1 << 4) /* Bit 4: Mode fault */
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#define SPI_TSR_ROVR (1 << 5) /* Bit 5: Read overrun */
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#define SPI_TSR_WCOL (1 << 6) /* Bit 6: Write collision */
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#define SPI_TSR_SPIF (1 << 7) /* Bit 7: SPI transfer complete */
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/* Bits 8-31: Reserved */
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/* SPI Interrupt Register */
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#define SPI_INT_SPIF (1 << 0) /* SPI interrupt */
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/* Bits 1-31: Reserved */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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/* These functions must be provided by the board specific logic that has knowledge
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* the chip select and card detect GPIO configuration of the board.
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*/
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void lpc23xx_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
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uint8_t lpc23xx_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
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#endif /* __ARCH_ARM_SRC_LPC2378_LPC23XX_SPI_H */
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