131 lines
4.2 KiB
C
131 lines
4.2 KiB
C
/****************************************************************************
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* boards/arm/stm32/stm3210e-eval/src/stm32_selectnor.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <debug.h>
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#include "chip.h"
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#include "arm_arch.h"
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#include "stm32.h"
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#include "stm3210e-eval.h"
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#ifdef CONFIG_STM32_FSMC
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#if STM32_NGPIO_PORTS < 6
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# error "Required GPIO ports not enabled"
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#endif
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* Pin Usage (per schematic)
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*
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* FLASH SRAM NAND LCD
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* D[0..15] [0..15] [0..15] [0..7] [0..15]
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* A[0..23] [0..22] [0..18] [16,17] [0]
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* FSMC_NBL0 PE0 OUT ~BLE --- --- ---
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* FSMC_NBL1 PE1 OUT ~BHE --- --- ---
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* FSMC_NE2 PG9 OUT --- ~E --- ---
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* FSMC_NE3 PG10 OUT ~CE --- --- ---
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* FSMC_NE4 PG12 OUT --- --- --- ~CS
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* FSMC_NWE PD5 OUT ~WE ~W ~W ~WR/SCL
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* FSMC_NOE PD4 OUT ~OE ~G ~R ~RD
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* FSMC_NWAIT PD6 IN --- R~B --- ---
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* FSMC_INT2 PG6* IN --- --- R~B ---
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*
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* *JP7 will switch to PD6
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*/
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/* GPIO configurations unique to NOR Flash */
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static const uint16_t g_norconfig[] =
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{
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/* A19... A22 */
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GPIO_NPS_A19, GPIO_NPS_A20, GPIO_NPS_A21, GPIO_NPS_A22,
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/* NE2 */
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GPIO_NPS_NE2
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};
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#define NNOR_CONFIG (sizeof(g_norconfig)/sizeof(uint16_t))
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_selectnor
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*
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* Description:
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* Initialize to access NOR flash
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*
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****************************************************************************/
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void stm32_selectnor(void)
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{
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/* Configure new GPIO state */
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stm32_extmemgpios(g_commonconfig, NCOMMON_CONFIG);
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stm32_extmemgpios(g_norconfig, NNOR_CONFIG);
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/* Enable AHB clocking to the FSMC */
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stm32_fsmc_enable();
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/* Bank1 NOR/SRAM control register configuration */
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putreg32(FSMC_BCR_NOR | FSMC_BCR_FACCEN |
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FSMC_BCR_MWID16 | FSMC_BCR_WREN,
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STM32_FSMC_BCR2);
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/* Bank1 NOR/SRAM timing register configuration */
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putreg32(FSMC_BTR_ADDSET(3) | FSMC_BTR_ADDHLD(1) |
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FSMC_BTR_DATAST(6) | FSMC_BTR_BUSTURN(1) |
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FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) |
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FSMC_BTR_ACCMODB, STM32_FSMC_BTR2);
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putreg32(0x0fffffff, STM32_FSMC_BWTR2);
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/* Enable the bank */
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putreg32(FSMC_BCR_MBKEN | FSMC_BCR_NOR |
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FSMC_BCR_FACCEN | FSMC_BCR_MWID16 |
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FSMC_BCR_WREN, STM32_FSMC_BCR2);
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}
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#endif /* CONFIG_STM32_FSMC */
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