cf8c25df64
This port was the joing effort of Janne Rosberg, Ivan Ucherdzhiev, and myself. I give credit to Ivan for the kill because he is the one to held on to the end.
Squashed commit of the following:
Author: Gregory Nutt <gnutt@nuttx.org>
configs/imxrt1050-evk/scripts: Add section to linker script to handle the case where RAMFUNCs are enabled. RAMFUNCs appear to be enabled in the default configuration ... they probably should not be enabled.
Author: Ivan Ucherdzhiev <ivanucherdjiev@gmail.com>
arch/arm/src/imxrt: imxrt_lowputc.c is finished. Now everything needed for the initial port is done and ready for testing.
arch/arm/src/imxrt: Add logic to imxrt_lowputc.c. Still incomplete.
Author: Ivan Ucherdzhiev <ivanucherdjiev@gmail.com>
arch/arm/src/imxrt: Add serial support. configs/imxrt1050-evk: Add linker script.
Author: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/imxrt: Add initial cut at imxrt_allocateheap.c
Author: Ivan Ucherdzhiev <ivanucherdjiev@gmail.com>
arm/arm/src/imxrt: Completes all definitions for PADMUX, CTLMUX, and IOMUX_INPUT and mapping tables on imxrt_gpio.c and imxr_iomuxc.c.
arch/arm/src/imxrt/chip: Add definitions for IMXRT_PADCTL and IMXRT_PADMUX registers. Only the IMXRT_INPUT definitions in this commit.
arch/arm/src/imxrt/chip: Add more IOMUXC register definitions.
Author: Gregory Nutt <gnutt@nuttx.org>
configs/imxrt1050-evk: Add STRIP definition to Make.defs.
arch/arm/src/imxrt: Bring in i.MX6 memory configuration settings.
arch/arm/src/imxrt: Remove call to non-existent imxrt_gpioinit() from imxrt_start.c.
arch/arm/src/imxrt: Bring in incomplete imxrt_iomuxc.c file from i.mx6.
arch/arm/src/imxrt: Add first cut at GPIO interrupt logic.
arch/arm/include: Add definitions to support a second level of GPIO pin interrupts.
Author: Janne Rosberg <janne.rosberg@offcode.fi>
arch/arm/src/imxrt: Add imxrt_wdog.c/.h
Author: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/imxrt: Port SAMv7 interrupt logic to imxrt_irq.c.
arch/arm/src/imxrt: More clarification of the start-up memory map.
arch/arm/src/imxrt: Some mostly cosmetic clean-up to the imxrt_start.c file that was so rudely taken from the SAMv7.
arch/arm/src/imxrt: Add imxrt_start.c. Initial commit is the the SAMv7 startup logic with name changes.
Author: Ivan Ucherdzhiev <ivanucherdjiev@gmail.com>
arch/arm/src/imxrt: Adds a few IOMUXC register definitions.
Author: Janne Rosberg <janne.rosberg@offcode.fi>
arch/arm/src/imxrt: Add imxrt_clockconfig.c/.h
configs/imxrt1050-evk: Add clock configuration definitions to board.h
arch/arm/src/imxrt: Fix CCM register name; Fix doubly defined in LPUART bit field.
arch/arm/src/imxrt: Add analog defines to CCM register definition header file.
Author: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/imxrt: Bring in GPIO C files from i.MX6. Things are in disarray now because that GPIO logic depends on IOMUXC logic which is not yet in place.
arch/arm/src/imxrt: Add a few more GPIO definitions to make the header file compatible with i.MX6
arch/arm/src/imxrt/chip: Add GPIO register definition file.
Author: Janne Rosberg <janne.rosberg@offcode.fi>
arch/arm/src/imxrt: Add DCDC register definitions.
arch/arm/srch/imxrt: Add CCM register bit definitions
Author: Gregory Nutt <gnutt@nuttx.org>
Purely cosmetic
arch/arm/src/imxrt: Add system reset controller register definition header file.
Embarassingly trivial change left in compiler.
arch/arm/src/imxrt: Finishes i.MX RT1050 LPUART register definition header file.
arch/arm/src/imxrt: Beginning of an i.MX RT1050 LPUART register definition header file.
Some trivial things
Author: Janne Rosberg <janne.rosberg@offcode.fi>
arch/arm/src/imxrt: Add imxrt_wdog.h
arch/arm/src/imxrt: Add initial imxrt_ccm.h
Author: Gregory Nutt <gnutt@nuttx.org>
Trivial update to README.
arch/arm/src/imxrt: The i.MX Rt implements 4 bits of interrupt priority, not two. Thanks, Janne.
arch/arm/src/imxrt: Fix some initial compile issues. Still a long way from complete, but there is a buildable environment now for the imxrt1050-evk.
configs/imxrt1050-evk: Add an initial NSH configuration for testing.
configs/Kconfig: Hook the i.MX RT 1050 board configuration into the NuttX configuration system.
configs/imxrt_evk: Add the framework for i.MX RT 1050 board support.
arch/arm/src/imxrt: Bring in a few more files from LPC54xxx.
arch/arm/src/imxrt: Bring in imxrt_clrpend() from the LPC54xxx.
arch/arm/src/imxrt: Bring in Cortex-M7 SysTick setup from the SAMv7.
arch/arm/src/imxrt: Add a few easy files.
arch/arm/src/imxrt/chip: Add memory map header files.
arch/arm/src/imxrt: A few basic files to start the port to the i.MX RT 1050.
140 lines
6.9 KiB
C
140 lines
6.9 KiB
C
/************************************************************************************
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* arch/arm/include/imxrt/chip.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_IMXRT_CHIP_H
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#define __ARCH_ARM_INCLUDE_IMXRT_CHIP_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Get customizations for each supported chip */
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/* MIMXRT1051CVL5A - Industrial, Reduced Features, 528MHz
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* MIMXRT1051CVL5A - Consumer, Reduced Features, 600MHz
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* MIMXRT1052CVL5A - Industrial, Full Feature, 528MHz
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* MIMXRT1052CVL5A - Consumer, Full Feature, 600MHz
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*/
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#if defined(CONFIG_ARCH_CHIP_MIMXRT1051DVL6A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1051CVL5A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1052DVL6A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1052CVL5A)
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#define IMXRT_OCRAM_SIZE (512 * 1024) /* 512Kb OCRAM */
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#else
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# error "Unknown i.MX RT chip type"
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#endif
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/* NVIC priority levels *************************************************************/
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/* Each priority field holds an 8-bit priority value, 0-15. The lower the value, the
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* greater the priority of the corresponding interrupt. The i.MX RT processor
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* implements only bits[7:4] of each field, bits[3:0] read as zero and ignore writes.
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*/
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#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is minimum priority */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */
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/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled
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* by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most
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* interrupts will not have execution priority. SVCall must have execution
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* priority in all cases.
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*
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* In the normal cases, interrupts are not nest-able and all interrupts run
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* at an execution priority between NVIC_SYSH_PRIORITY_MIN and
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* NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall).
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*
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* If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special
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* high priority interrupts are supported. These are not "nested" in the
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* normal sense of the word. These high priority interrupts can interrupt
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* normal processing but execute outside of OS (although they can "get back
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* into the game" via a PendSV interrupt).
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*
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* In the normal course of things, interrupts must occasionally be disabled
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* using the up_irq_save() inline function to prevent contention in use of
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* resources that may be shared between interrupt level and non-interrupt
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* level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT,
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* do we disable all interrupts (except SVCall), or do we only disable the
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* "normal" interrupts. Since the high priority interrupts cannot interact
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* with the OS, you may want to permit the high priority interrupts even if
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* interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be
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* used to select either behavior:
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*
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* ----------------------------+--------------+----------------------------
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* CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES
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* ----------------------------+--------------+--------------+-------------
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* CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO
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* ----------------------------+--------------+--------------+-------------
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* | | | SVCall
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* | SVCall | SVCall | HIGH
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* Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL
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* | | MAXNORMAL |
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* ----------------------------+--------------+--------------+-------------
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*/
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#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL)
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# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP)
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# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
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# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY
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# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
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#else
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# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
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# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX
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# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY
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# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
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#endif
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_INCLUDE_IMXRT_CHIP_H */
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