d1c406d65d
When starting dma transfer, the dcache for the TX buffer should be cleaned. "flush" performs also invalidate, which is unnecessary. The TX buffer can be unaligned to the cahche line in some(most) cases, whereas RX buffer can never be. The cache for the receive buffer can be dirty and valid before call to exchange. Thus another memory access (hitting the same cache line) may corrupt receive data while waiting for transfer to complete. So the receive buffer should be invalidated before the transfer Signed-off-by: Jukka Laitinen <jukka.laitinen@intel.com> |
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| Kconfig | ||