163 lines
9.9 KiB
C
163 lines
9.9 KiB
C
/************************************************************************************************
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* arch/arm/src/sam34/chip/sam4l_memorymap.h
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_MEMORYMAP_H
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#define __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_MEMORYMAP_H
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/************************************************************************************************
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* Included Files
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************************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************************
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* Pre-processor Definitions
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************************************************************************************************/
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/* Global Memory Space */
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#define SAM_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: Code space */
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#define SAM_INTSRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: Internal SRAM */
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/* 0x22000000-0x3fffffff: Undefined */
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#define SAM_PERIPHERALS_BASE 0x40000000 /* 0x40000000-0x5fffffff: Peripherals */
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/* 0x60000000-0xdfffffff: Reserved */
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#define SAM_SYSTEM_BASE 0xe0000000 /* 0xe0000000-0xffffffff: System */
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/* Code Space */
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#define SAM_INTFLASH_BASE 0x00000000 /* 0x00000000-0x003fffff: Internal FLASH */
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/* 0x00400000-0x1fffffff: Reserved */
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/* Internal SRAM Space */
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#define SAM_INTSRAM0_BASE 0x20000000 /* 0x20000000-0x2007ffff: HRAMC0 (see chip.h) */
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/* 0x20008000-0x20ffffff: Reserved */
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#define SAM_INTSRAM1_BASE 0x21000000 /* 0x21000000-0x210007ff: HRAMC1 (see chip.h) */
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/* 0x21000800-0x21ffffff: Reserved */
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/* Peripherals Space */
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#define SAM_PERIPHA_BASE 0x40000000 /* 0x40000000-0x4009ffff: Peripheral Bridge A */
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#define SAM_PERIPHB_BASE 0x400a0000 /* 0x400a0000-0x400affff: Peripheral Bridge B */
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#define SAM_AESA_BASE 0x400b0000 /* 0x400b0000-0x400b00ff: AESA */
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/* 0x400b0100-0x400dffff: Reserved */
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#define SAM_PERIPHC_BASE 0x400e0000 /* 0x400e0000-0x400effff: Peripheral Bridge C */
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#define SAM_PERIPHD_BASE 0x400e0000 /* 0x400f0000-0x400fffff: Peripheral Bridge D */
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/* 0x40100000-0x5fffffff: Reserved */
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/* Peripheral Bridge A */
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/* 0x40000000-0x40003fff: Reserved */
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#define SAM_I2SC_BASE 0x40004000 /* 0x40004000-0x40007fff: I2S Controller */
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#define SAM_SPI0_BASE 0x40008000 /* 0x40008000-0x4000bfff: Serial Peripheral Interface */
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/* 0x4000c000-0x4000ffff: Reserved */
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#define SAM_TC0_BASE 0x40100000 /* 0x40100000-0x4013ffff: Timer Counter 0 */
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#define SAM_TC1_BASE 0x40140000 /* 0x40180000-0x4017ffff: Timer Counter 1 */
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#define SAM_TWIMS0_BASE 0x40180000 /* 0x40180000-0x401bffff: Two-wire Master/Slave Interface 0 */
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#define SAM_TWIMS1_BASE 0x401c0000 /* 0x401c0000-0x401fffff: Two-wire Master/Slave Interface 1 */
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/* 0x40020000-0x40023fff: Reserved */
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#define SAM_USARTN_BASE(n) (0x40024000+((n)<<14))
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#define SAM_USART0_BASE 0x40024000 /* 0x40024000-0x40027fff: USART0 */
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#define SAM_USART1_BASE 0x40028000 /* 0x40028000-0x4002bfff: USART1 */
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#define SAM_USART2_BASE 0x4002c000 /* 0x4002c000-0x4002ffff: USART2 */
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#define SAM_USART3_BASE 0x40030000 /* 0x40030000-0x40033fff: USART3 */
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/* 0x40034000-0x40037fff: Reserved */
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#define SAM_ADCIFE_BASE 0x40038000 /* 0x40038000-0x4003bfff: ADC controller interface */
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#define SAM_DACC_BASE 0x4003c000 /* 0x4003c000-0x4003ffff: DAC Controller */
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#define SAM_ACIF_BASE 0x40040000 /* 0x40040000-0x40043fff: Analog Comparator Interface */
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/* 0x40044000-0x4005ffff: Reserved */
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#define SAM_GLOC_BASE 0x40040000 /* 0x40060000-0x40063fff: GLOC */
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#define SAM_ABDACB_BASE 0x40040000 /* 0x40064000-0x40067fff: Audio Bitstream DAC */
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#define SAM_TRNG_BASE 0x40068000 /* 0x40064000-0x4006bfff: True Random Number Generator */
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#define SAM_PARC_BASE 0x4006c000 /* 0x4006c000-0x4006ffff: Parallel Capture */
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#define SAM_CATB_BASE 0x40070000 /* 0x4006c000-0x40073fff: Capacitive Touch Module B */
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/* 0x40074000-0x40077fff: Reserved */
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#define SAM_TWIM2_BASE 0x40078000 /* 0x40078000-0x4007bfff: Two-wire Master Interface 2 */
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#define SAM_TWIM3_BASE 0x4007c000 /* 0x4007c000-0x4007ffff: Two-wire Master Interface 3 */
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#define SAM_LCDCA_BASE 0x40080000 /* 0x40080000-0x40083fff: LCD Controller A */
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/* 0x40084000-0x4009ffff: Reserved */
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/* Peripheral Bridge B */
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#define SAM_FLASHCALW_BASE 0x400a0000 /* 0x400a0000-0x400a03ff: FLASHCALW */
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#define SAM_PICOCACHE_BASE 0x400a0400 /* 0x400a0400-0x400a0fff: PICOCACHE */
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#define SAM_HMATRIX_BASE 0x400a1000 /* 0x400a1000-0x400a1fff: HMATRIX */
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#define SAM_PDCA_BASE 0x400a2000 /* 0x400a2000-0x400a2fff: Peripheral DMA Controller */
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#define SAM_SMAP_BASE 0x400a3000 /* 0x400a3000-0x400a3fff: SMAP */
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#define SAM_CRCCU_BASE 0x400a4000 /* 0x400a4000-0x400a4fff: CRC Calculation Unit */
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#define SAM_USBC_BASE 0x400a5000 /* 0x400a5000-0x400a5fff: USB 2.0 Interface */
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#define SAM_PEVC_BASE 0x400a6000 /* 0x400a6000-0x400a63ff: Peripheral Event Controller */
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/* 0x400a6400-0x400affff: Reserved */
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/* Peripheral Bridge C */
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#define SAM_PM_BASE 0x400e0000 /* 0x400e0000-0x400e073f: Power Manager */
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#define SAM_CHIPID_BASE 0x400e0740 /* 0x400e0740-0x400e07ff: CHIPID */
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#define SAM_SCIF_BASE 0x400e0800 /* 0x400e0800-0x400e0bff: System Control Interface */
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#define SAM_FREQM_BASE 0x400e0c00 /* 0x400e0c00-0x400e0fff: Frequency Meter */
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#define SAM_GPIO_BASE 0x400e1000 /* 0x400e1000-0x400e17ff: GPIO */
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/* 0x400e1800-0x400effff: Reserved */
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/* Peripheral Bridge D */
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#define SAM_BPM_BASE 0x400f0000 /* 0x400f0000-0x400f03ff: Backup Power Manager */
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#define SAM_BSCIF_BASE 0x400f0400 /* 0x400f0400-0x400f07ff: Backup System Control Interface */
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#define SAM_AST_BASE 0x400f0800 /* 0x400f0800-0x400f0bff: Asynchronous Timer */
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#define SAM_WDT_BASE 0x400f0c00 /* 0x400f0c00-0x400f0fff: Watchdog Timer */
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#define SAM_EIC_BASE 0x400f1000 /* 0x400f1000-0x400f13ff: External Interrupt Controller */
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#define SAM_PICOUART_BASE 0x400f1400 /* 0x400f1400-0x400f17ff: PICOUART */
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/* 0x400f1800-0x400fffff: Reserved */
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/* System Space */
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#define SAM_ITM_BASE 0xe0000000 /* 0xe0000000-0xe0000fff: ITM */
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#define SAM_DWT_BASE 0xe0001000 /* 0xe0001000-0xe0001fff: DWT */
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#define SAM_FPB_BASE 0xe0002000 /* 0xe0002000-0xe0002fff: FPB */
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/* 0xe0003000-0xe000dfff: Reserved */
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#define SAM_SCS_BASE 0xe000e000 /* 0xe000e000-0xe000efff: SCS */
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/* 0xe000f000-0xe003ffff: Reserved */
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#define SAM_TPIU_BASE 0xe0040000 /* 0xe0040000-0xe0040fff: TPIU */
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/* 0xe0041000-0xe0041fff: Reserved */
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#define SAM_EXTPPB_BASE 0xe0042000 /* 0xe0042000-0xe00fefff: External PPB */
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#define SAM_ROMTAB_BASE 0xe00ff000 /* 0xe00ff000-0xe00fffff: ROM Table */
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/* 0xe0100000-0xffffffff: Reserved */
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/************************************************************************************************
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* Public Types
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************************************************************************************************/
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/************************************************************************************************
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* Public Data
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************************************************************************************************/
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/************************************************************************************************
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* Public Functions
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************************************************************************************************/
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#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM4L_MEMORYMAP_H */
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