06f132c5d0
Squashed commit of the following:
Update a README. Mark MAX326XX as EXPERIMENTAL before bringing into master.
arch/arm/src/max326xx/chip: Add MAX32660 TMR register definition header files.
arch/arm/src/max326xx/chip: Add MAX32660 WDT register definition header files.
arch/arm/src/max326xx/chip: Add MAX32660 RTC register definition header files.
arch/arm/src/max326xx/chip: Add MAX32660 UART register definition header files.
arch/arm/src/max326xx/chip: Add DMA register definition header files.
Update some comments explaining what is meant by a 'chip family'
arch/arm/src/max326xx/chip: Add GPIO register definition header files.
arch/arm/src/max326xx/chip: Add FLC register definition header files.
arch/arm/src/max326xx/chip: Add FCR, PWRSEQ, and SIR register definition header files.
arch/arm/src/max326xx/chip: Add ICC register definition header file.
arch/arm/src/max326xx/chip: Add memory map header files.
arch/arm/include/max326xx: Minor fleshing out.
arch/arm/arm/include/max326xx: Add basic support for Maxim MAX326xx family. arch/arm/Kconfig and arch/arm/src/max326xx/Kconfig: Add basic condiguration support for the MAX326xx.
216 lines
10 KiB
C
216 lines
10 KiB
C
/************************************************************************************
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* arch/arm/include/max326xx/chip.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_MAX326XX_CHIP_H
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#define __ARCH_ARM_INCLUDE_MAX326XX_CHIP_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Get customizations for each supported MAX326xx family. Only sizes and numbers of
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* things are provided here. See arch/arm/src/max326xx/Kconfig for other, boolean
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* configuration settings.
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*
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* MAX326xx Families are determined by sharing a common User Guide for the chip
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* specification:
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*
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* MAX32620/32621 Family: MAX32620 Rev C, User Guide, AN6242, Rev 2, 2/17
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* MAX32630/32632 Family: MAX32630 Rev B, User Guide, AN6349, Rev 0, 10/16
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* MAX32660 Family: MAX32660 User Guide, AN6659, Rev0, 7/18
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*/
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/* MAX32620/32621 Family:
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*
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* Part Flash SRAM Trust Pin/Package
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* (Mb) (Kb) Protection
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* MAX32620ICQ+ 2 256 No 100 TQFP
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* MAX32620IWG+ 2 256 No 81 WLP
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* MAX32620IWG+T 2 256 No 81 WLP
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* MAX32620IWGL+ 1 256 No 81 WLP
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* MAX32620IWGL+T 1 256 No 81 WLP
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* MAX32621ICQ+ 2 256 Yes 100 TQFP
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* MAX32621IWG+ 2 256 Yes 81 WLP
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* MAX32621IWG+T 2 256 Yes 81 WLP
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*/
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#if defined(CONFIG_ARCH_CHIP_MAX32620) || defined(CONFIG_ARCH_CHIP_MAX32621)
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/* Peripherals */
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# define MAX326_NWDOG 0 /* No Watchog Timers */
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# define MAX326_NWWDOG 2 /* Two Windowed Watchog Timers */
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# define MAX326_NRWDOG 1 /* One Recovery Watchog Timer */
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# define MAX326_NWAKEUP 1 /* One Wakeup Timer */
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# define MAX326_NRTC 1 /* One RTC */
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# define MAX326_NCRC 1 /* One CRC16/32 */
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# define MAX326_NAES 1 /* One AES 128,192, 256 */
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# define MAX326_NUSB20 1 /* One USB 2.0 device */
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# define MAX326_NTMR32 6 /* Six 32-bit Timers */
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# define MAX326_NTMR8 0 /* No 8-bit Timers */
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# define MAX326_NPTENGINE 16 /* Sixteen pulse train engines */
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# define MAX326_NSPIM 3 /* Three SPI master */
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# define MAX326_NSPIS 1 /* One SPI slave */
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# define MAX326_NSPIXIP 1 /* One SPI XIP */
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# define MAX326_NI2SS 0 /* No I2S slave */
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# define MAX326_NI2CM 3 /* Three I2C master */
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# define MAX326_NI2CS 1 /* One I2C slave */
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# define MAX326_NUART 4 /* Four UARTs */
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# define MAX326_N1WIREM 1 /* One 1-Wire master */
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# define MAX326_NADC10 1 /* One 10-bit ADC */
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/* MAX32630/32632 Family:
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*
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* Part Flash SRAM Trust Secure Pin/Package
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* (Mb) (Kb) Protection Bootloader
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* MAX32630IWQ+ 2 512 No No 100 WLP
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* MAX32630IWQ+T 2 512 No No 100 WLP
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* MAX32630ICQ+ 2 512 No No 100 TQFP-EP
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* MAX32631IWQ+ 2 512 Yes No 100 WLP
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* MAX32631IWQ+T 2 512 Yes No 100 WLP
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* MAX32631ICQ+ 2 512 Yes No 100 TQFP-EP
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* MAX32632IWQ+ 2 512 Yes Yes 100 WLP
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* MAX32632IWQ+T 2 512 Yes Yes 100 WLP
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*/
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#elif defined(CONFIG_ARCH_CHIP_MAX32630) || defined(CONFIG_ARCH_CHIP_MAX32632)
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/* Peripherals */
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# define MAX326_NWDOG 0 /* No Watchog Timers */
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# define MAX326_NWWDOG 2 /* Two Windowed Watchog Timers */
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# define MAX326_NRWDOG 0 /* No Recovery Watchog Timer */
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# define MAX326_NWAKEUP 1 /* One Wakeup Timer */
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# define MAX326_NRTC 1 /* One RTC */
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# define MAX326_NCRC 1 /* One CRC16/32 */
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# define MAX326_NAES 1 /* One AES 128,192, 256 */
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# define MAX326_NUSB20 1 /* One USB 2.0 device */
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# define MAX326_NTMR32 6 /* Six 32-bit Timers */
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# define MAX326_NTMR8 0 /* No 8-bit Timers */
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# define MAX326_NPTENGINE 16 /* Sixteen pulse train engines */
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# define MAX326_NSPIM 3 /* Three SPI master */
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# define MAX326_NSPIS 1 /* One SPI slave */
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# define MAX326_NSPIXIP 1 /* One SPI XIP */
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# define MAX326_NI2SS 0 /* No I2S slave */
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# define MAX326_NI2CM 3 /* Three I2C master */
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# define MAX326_NI2CS 1 /* One I2C slave */
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# define MAX326_NUART 4 /* Four UARTs */
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# define MAX326_N1WIREM 1 /* One 1-Wire master */
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# define MAX326_NADC10 1 /* One 10-bit ADC */
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/* MAX32660 Family:
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*
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* Part Flash SRAM Secure Pin/Package
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* (Mb) (Kb) Bootloader
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* MAX32660GWE+ 256 96 No 16 WLP
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* MAX32660GWE+T 256 96 No 16 WLP
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* MAX32660GTP+ 256 96 No 20 TQFN-EP
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* MAX32660GTP+T 256 96 No 20 TQFN-EP
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* MAX32660GTG+ 256 96 No 24 TQFN-EP
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* MAX32660GTG+T 256 96 No 24 TQFN-EP
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* MAX32660GWEBL+* 256 96 Yes 16 WLP
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* MAX32660GWEBL+T* 256 96 Yes 16 WLP
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* MAX32660GTGBL+* 256 96 Yes 24 TQFN-EP
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* MAX32660GTGBL+T* 256 96 Yes 24 TQFN-EP
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* MAX32660GWELA+* 128 64 No 16 WLP
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* MAX32660GWELA+T* 128 64 No 16 WLP
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* MAX32660GTGLA+* 128 64 No 24 TQFN-EP
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* MAX32660GTGLA+T* 128 64 No 24 TQFN-EP
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* MAX32660GWELB+* 64 32 No 16 WLP
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* MAX32660GWELB+T* 64 32 No 16 WLP
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* MAX32660GTGLB+* 64 32 No 24 TQFN-EP
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* MAX32660GTGLB+T* 64 32 No 24 TQFN-EP
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*/
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#elif defined(CONFIG_ARCH_CHIP_MAX32660)
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/* Peripherals */
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# define MAX326_NWDOG 1 /* One Watchog Timer */
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# define MAX326_NWWDOG 0 /* No Windowed Watchog Timers */
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# define MAX326_NRWDOG 0 /* No Recovery Watchog Timer */
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# define MAX326_NWAKEUP 0 /* No Wakeup Timer */
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# define MAX326_NRTC 1 /* One RTC */
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# define MAX326_NCRC 0 /* No CRC16/32 */
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# define MAX326_NAES 0 /* No AES 128,192, 256 */
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# define MAX326_NUSB20 0 /* No USB 2.0 device */
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# define MAX326_NTMR32 2 /* Two 32-bit Timers */
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# define MAX326_NTMR8 1 /* One 8-bit Timers */
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# define MAX326_NPTENGINE 0 /* No pulse train engines */
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# define MAX326_NSPIM 2 /* Three SPI master */
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# define MAX326_NSPIS 2 /* Two SPI slave */
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# define MAX326_NSPIXIP 0 /* No SPI XIP */
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# define MAX326_NI2SS 1 /* One I2S slave */
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# define MAX326_NI2CM 2 /* Two I2C master */
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# define MAX326_NI2CS 2 /* One I2C slave */
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# define MAX326_NUART 2 /* Two UARTs */
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# define MAX326_N1WIREM 0 /* No 1-Wire master */
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# define MAX326_NADC10 0 /* No 10-bit ADC */
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#else
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# error Unrecognized MAX326XX chip
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#endif
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/* NVIC priority levels *************************************************************/
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/* Each priority field holds a priority value, 0x00-0xe0. The lower the value, the
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* greater the priority of the corresponding interrupt. The processor implements only
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* bits[7:4] of each field, bits[6:0] read as zero and ignore writes.
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*/
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#define NVIC_SYSH_PRIORITY_MIN 0xe0 /* All bits[7:5] set is minimum priority */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x20 /* Eight priority levels in steps 0x20 */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_INCLUDE_MAX326XX_CHIP_H */
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