155 lines
7.6 KiB
C
155 lines
7.6 KiB
C
/****************************************************************************
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* arch/mips/src/pic32mx/pic32mx_osc.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_OSC_H
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#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_OSC_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "pic32mx_memorymap.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register Offsets *********************************************************/
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#define PIC32MX_OSCCON_OFFSET 0x0000 /* Oscillator control register offset */
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#define PIC32MX_OSCTUN_OFFSET 0x0010 /* FRC tuning register offset */
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/* Register Addresses *******************************************************/
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#define PIC32MX_OSCCON (PIC32MX_OSC_K1BASE+PIC32MX_OSCCON_OFFSET)
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#define PIC32MX_OSCTUN (PIC32MX_OSC_K1BASE+PIC32MX_OSCTUN_OFFSET)
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/* Register Bit-Field Definitions *******************************************/
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/* Oscillator control register offset */
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#define OSCCON_OSWEN (1 << 0) /* Bit 0: Oscillator switch enable */
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#define OSCCON_SOSCEN (1 << 1) /* Bit 1: 32.768kHz secondary oscillator enable */
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#define OSCCON_UFRCEN (1 << 2) /* Bit 2: USB FRC clock enable */
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#define OSCCON_CF (1 << 3) /* Bit 3: Clock fail detect */
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#define OSCCON_SLPEN (1 << 4) /* Bit 4: Sleep mode enable */
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#define OSCCON_SLOCK (1 << 5) /* Bit 5: PLL lock status */
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#define OSCCON_ULOCK (1 << 6) /* Bit 6: USB PLL lock status */
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#define OSCCON_CLKLOCK (1 << 7) /* Bit 7: Clock selection lock enable */
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#define OSCCON_NOSC_SHIFT (8) /* Bits 8-10: New oscillator selection */
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#define OSCCON_NOSC_MASK (7 << OSCCON_NOSC_SHIFT)
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# define OSCCON_NOSC_FRC (0 << OSCCON_NOSC_SHIFT) /* FRC oscillator */
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# define OSCCON_NOSC_FRCPLL (1 << OSCCON_NOSC_SHIFT) /* FRC w/PLL postscaler */
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# define OSCCON_NOSC_POSC (2 << OSCCON_NOSC_SHIFT) /* Primary oscillator */
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# define OSCCON_NOSC_POSCPLL (3 << OSCCON_NOSC_SHIFT) /* Primary oscillator with PLL */
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# define OSCCON_NOSC_SOSC (4 << OSCCON_NOSC_SHIFT) /* Secondary oscillator */
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# define OSCCON_NOSC_LPRC (5 << OSCCON_NOSC_SHIFT) /* Low power RC oscillator */
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# define OSCCON_NOSC_FRCDIV16 (6 << OSCCON_NOSC_SHIFT) /* FRC divided by 16 */
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# define OSCCON_NOSC_FRCDIV (7 << OSCCON_NOSC_SHIFT) /* FRC dived by FRCDIV */
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#define OSCCON_COSC_SHIFT (12) /* Bits 12-14: Current oscillator selection */
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#define OSCCON_COSC_MASK (7 << OSCCON_COSC_SHIFT)
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# define OSCCON_COSC_FRC (0 << OSCCON_COSC_SHIFT) /* FRC oscillator */
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# define OSCCON_COSC_FRCPLL (1 << OSCCON_COSC_SHIFT) /* FRC w/PLL postscaler */
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# define OSCCON_COSC_POSC (2 << OSCCON_COSC_SHIFT) /* Primary oscillator */
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# define OSCCON_COSC_POSCPLL (3 << OSCCON_COSC_SHIFT) /* Primary oscillator with PLL */
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# define OSCCON_COSC_SOSC (4 << OSCCON_COSC_SHIFT) /* Secondary oscillator */
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# define OSCCON_COSC_LPRC (5 << OSCCON_COSC_SHIFT) /* Low power RC oscillator */
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# define OSCCON_COSC_FRCDIV16 (6 << OSCCON_COSC_SHIFT) /* FRC divided by 16 */
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# define OSCCON_COSC_FRCDIV (7 << OSCCON_COSC_SHIFT) /* FRC dived by FRCDIV */
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#define OSCCON_PLLMULT_SHIFT (16) /* Bits 16-18: PLL multiplier */
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#define OSCCON_PLLMULT_MASK (7 << OSCCON_PLLMULT_SHIFT)
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# define OSCCON_PLLMULT_MUL15 (0 << OSCCON_PLLMULT_SHIFT)
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# define OSCCON_PLLMULT_MUL16 (1 << OSCCON_PLLMULT_SHIFT)
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# define OSCCON_PLLMULT_MUL17 (2 << OSCCON_PLLMULT_SHIFT)
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# define OSCCON_PLLMULT_MUL18 (3 << OSCCON_PLLMULT_SHIFT)
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# define OSCCON_PLLMULT_MUL19 (4 << OSCCON_PLLMULT_SHIFT)
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# define OSCCON_PLLMULT_MUL20 (5 << OSCCON_PLLMULT_SHIFT)
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# define OSCCON_PLLMULT_MUL21 (6 << OSCCON_PLLMULT_SHIFT)
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# define OSCCON_PLLMULT_MUL24 (7 << OSCCON_PLLMULT_SHIFT)
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#define OSCCON_PBDIV_SHIFT (19) /* Bits 19-20: PBVLK divisor */
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#define OSCCON_PBDIV_SMASK (3 << OSCCON_PBDIV_SHIFT)
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# define OSCCON_PBDIV_DIV1 (0 << OSCCON_PBDIV_SHIFT)
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# define OSCCON_PBDIV_DIV2 (1 << OSCCON_PBDIV_SHIFT)
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# define OSCCON_PBDIV_DIV4 (2 << OSCCON_PBDIV_SHIFT)
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# define OSCCON_PBDIV_DIV8 (3 << OSCCON_PBDIV_SHIFT)
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#define OSCCON_SOSCRDY (1 << 22) /* Bit 22: Secondary oscillator ready */
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#define OSCCON_FRCDIV_SHIFT (24) /* Bits 24-26: FRC oscillator divider */
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#define OSCCON_FRCDIV_MASK (7 << OSCCON_FRCDIV_SHIFT)
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# define OSCCON_FRCDIV_DIV1 (0 << OSCCON_FRCDIV_SHIFT)
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# define OSCCON_FRCDIV_DIV2 (1 << OSCCON_FRCDIV_SHIFT)
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# define OSCCON_FRCDIV_DIV4 (2 << OSCCON_FRCDIV_SHIFT)
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# define OSCCON_FRCDIV_DIV8 (3 << OSCCON_FRCDIV_SHIFT)
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# define OSCCON_FRCDIV_DIV16 (4 << OSCCON_FRCDIV_SHIFT)
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# define OSCCON_FRCDIV_DIV32 (5 << OSCCON_FRCDIV_SHIFT)
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# define OSCCON_FRCDIV_DIV64 (6 << OSCCON_FRCDIV_SHIFT)
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# define OSCCON_FRCDIV_DIV256 (7 << OSCCON_FRCDIV_SHIFT)
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#define OSCCON_PLL0DIV_SHIFT (27) /* Bits 27-29: Output divider for PLL */
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#define OSCCON_PLL0DIV_MASK (7 << OSCCON_PLL0DIV_SHIFT)
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# define OSCCON_PLL0DIV_DIV1 (0 << OSCCON_PLL0DIV_SHIFT)
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# define OSCCON_PLL0DIV_DIV2 (1 << OSCCON_PLL0DIV_SHIFT)
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# define OSCCON_PLL0DIV_DIV4 (2 << OSCCON_PLL0DIV_SHIFT)
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# define OSCCON_PLL0DIV_DIV8 (3 << OSCCON_PLL0DIV_SHIFT)
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# define OSCCON_PLL0DIV_DIV16 (4 << OSCCON_PLL0DIV_SHIFT)
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# define OSCCON_PLL0DIV_DIV32 (5 << OSCCON_PLL0DIV_SHIFT)
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# define OSCCON_PLL0DIV_DIV64 (6 << OSCCON_PLL0DIV_SHIFT)
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# define OSCCON_PLL0DIV_DIV256 (7 << OSCCON_PLL0DIV_SHIFT)
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/* FRC tuning register offset (6-bit, signed twos complement) */
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#define OSCTUN_SHIFT (0) /* Bits 0-5: FRC tuning bits */
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#define OSCTUN_MASK (0x3f << OSCTUN_SHIFT)
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# define OSCTUN_MIN (0x20 << OSCTUN_SHIFT)
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# define OSCTUN_CENTER (0x00 << OSCTUN_SHIFT)
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# define OSCTUN_MAX (0x1f << OSCTUN_SHIFT)
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/****************************************************************************
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* Inline Functions
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_OSC_H */
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