d42fc094fa
arm: stm32: codestyle fixes
* arm: stm32f0l0g0: codestyle fixes
After the board restructuration is time for codestyle cleanup
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arm: stm32f7: codestyle fixes
After the board restructuration is time for codestyle cleanup
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arm: stm32h7: codestyle fixes
After the board restructuration is time for codestyle cleanup
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arm: stm32l4: codestyle fixes
After the board restructuration is time for codestyle cleanup
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arm: stm32: codestyle fixes
After the board restructuration is time for codestyle cleanup
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
269 lines
10 KiB
C
269 lines
10 KiB
C
/****************************************************************************
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* boards/arm/stm32/omnibusf4/include/board.h
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*
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* Copyright (C) 2019 Bill Gatliff. All Rights reserved.
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* Copyright (C) 2012, 2014-2016, 2018 Gregory Nutt. All rights reserved.
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* Author: Bill Gatliff <bgat@billgatliff.com>
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_STM32_OMNIBUSF4_INCLUDE_BOARD_H
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#define __BOARDS_ARM_STM32_OMNIBUSF4_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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# include <stdbool.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *************************************************************************/
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/* The OMNIBUSF4 board uses a single 8MHz crystal.
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*
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* This is the canonical configuration:
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* System Clock source : PLL (HSE)
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* SYSCLK(Hz) : 168000000 Determined by PLL configuration
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* HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE)
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* AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE)
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* APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1)
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* APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2)
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* HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL)
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* PLLM : 8 (STM32_PLLCFG_PLLM)
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* PLLN : 336 (STM32_PLLCFG_PLLN)
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* PLLP : 2 (STM32_PLLCFG_PLLP)
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* PLLQ : 7 (STM32_PLLCFG_PLLQ)
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* Main regulator output voltage : Scale1 mode Needed for high speed SYSCLK
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* Flash Latency(WS) : 5
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* Prefetch Buffer : OFF
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* Instruction cache : ON
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* Data cache : ON
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* Require 48MHz for USB OTG FS, : Enabled
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* SDIO and RNG clock
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*/
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/* HSI - 16 MHz RC factory-trimmed
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* LSI - 32 KHz RC
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* HSE - On-board crystal frequency is 8MHz
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* LSE - 32.768 kHz
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*/
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#define STM32_BOARD_XTAL 8000000ul
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#define STM32_HSI_FREQUENCY 16000000ul
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#define STM32_LSI_FREQUENCY 32000
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_LSE_FREQUENCY 32768
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/* Main PLL Configuration.
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*
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* PLL source is HSE
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* PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
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* = (8,000,000 / 8) * 336
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* = 336,000,000
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* SYSCLK = PLL_VCO / PLLP
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* = 336,000,000 / 2 = 168,000,000
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* USB OTG FS, SDIO and RNG Clock
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* = PLL_VCO / PLLQ
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* = 48,000,000
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*/
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336)
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
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#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7)
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#define STM32_SYSCLK_FREQUENCY 168000000ul
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/* AHB clock (HCLK) is SYSCLK (168MHz) */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
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/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
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/* Timers driven from APB1 will be twice PCLK1 */
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
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/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* Timers driven from APB2 will be twice PCLK2 */
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#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY)
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
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* otherwise frequency is 2xAPBx.
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* Note: TIM1,8 are on APB2, others on APB1
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*/
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#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
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#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
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#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
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#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
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#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
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#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
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#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY
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/* Pin configurations **************************************************************/
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#define BOARD_NLEDS 2 /* One literal LED, one beeper */
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#define GPIO_LED1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz |\
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GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN5)
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#define GPIO_BEEPER1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz |\
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GPIO_OUTPUT_CLEAR | GPIO_PORTB|GPIO_PIN4)
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/* USART1: */
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#if 0
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#define INVERTER_PIN_USART1 PC0 /* DYS F4 Pro, Omnibus F4 AIO 1st Gen only */
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#endif
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#define GPIO_USART1_RX GPIO_USART1_RX_1 /* PA10 */
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#define GPIO_USART1_TX GPIO_USART1_TX_1 /* PA9 */
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/* USART2:
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*
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* TODO: Do OMNIBUSF4 targets use USART2?
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*/
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/* USART3: */
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#define GPIO_USART3_TX GPIO_USART3_TX_1 /* PB10 */
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#define GPIO_USART3_RX GPIO_USART3_RX_1 /* PB11 */
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/* USART4: */
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/* USART6: */
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#if 0
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#define INVERTER_PIN_UART6 PC8 /* Omnibus F4 V3 and later, EXUAVF4PRO */
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#endif
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#define GPIO_USART6_RX GPIO_USART6_RX_1 /* PC7 */
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#define GPIO_USART6_TX GPIO_USART6_TX_1 /* PC6 */
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/* PWM - motor outputs, etc. are on these pins: */
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#define GPIO_TIM3_CH3OUT GPIO_TIM3_CH3OUT_1 /* S1_OUT PB0 */
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#define GPIO_TIM3_CH4OUT GPIO_TIM3_CH4OUT_1 /* S2_OUT PB1 */
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#define GPIO_TIM2_CH4OUT GPIO_TIM2_CH4OUT_1 /* S3_OUT PA3 */
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#define GPIO_TIM2_CH3OUT GPIO_TIM3_CH3OUT_1 /* S4_OUT PA2 */
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/* SPI1 :
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*
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* MPU6000 6-axis motion sensor (accelerometer + gyroscope), or
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* MPU6500 6-Axis MEMS MotionTracking Device with DMP
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*
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* MPU6000 interrupts
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* #define USE_GYRO_EXTI
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* #define GYRO_1_EXTI_PIN PC4
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* #define USE_MPU_DATA_READY_SIGNAL
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*
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* #define GYRO_1_ALIGN CW270_DEG
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* #define ACC_1_ALIGN CW270_DEG
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*/
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#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 /* PA6 */
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#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1 /* PA7 */
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#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 /* PA5 */
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#if 0
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#define GPIO_SPI1_NSS GPIO_SPI1_NSS_2 /* PA4 */
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#endif
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#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 /* 2:0:3 */
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#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 /* 2:3:3 */
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/* SPI2 :
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*
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* Used for MMC/SD on OMNIBUSF4SD.
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*/
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#define GPIO_SPI2_MISO GPIO_SPI2_MISO_1 /* PB14 */
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#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1 /* PB15 */
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#define GPIO_SPI2_NSS (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \
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GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN12)
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#define GPIO_SPI2_SCK GPIO_SPI2_SCK_2 /* PB13 */
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#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX /* 1:3:0 */
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#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX /* 1:4:0 */
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#define GPIO_MMCSD_NSS GPIO_SPI2_NSS
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#define GPIO_MMCSD_NCD (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | \
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GPIO_PORTB | GPIO_PIN7) /* PB7 SD_DET */
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/* SPI3 :
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*
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* OMNIBUSF4SD targets use PA15 for NSS; others use PB4 (? BF code says "PB3").
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* define GPIO_SPI3_NSS GPIO_SPI3_NSS_2 PB4
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*
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* Barometer and/or MAX7456, depending on the target.
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* (OMNIBUSF4BASE targets appear to have a cyrf6936 device.)
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*/
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#define GPIO_SPI3_MISO GPIO_SPI3_MISO_2 /* PC11 */
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#define GPIO_SPI3_MOSI GPIO_SPI3_MOSI_2 /* PC12 */
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#define GPIO_SPI3_NSS GPIO_SPI3_NSS_1 /* PA15 */ /* TODO: doesn't work like a chip select */
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#define GPIO_SPI3_SCK GPIO_SPI3_SCK_2 /* PC10 */
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#if 0
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/* I2C : */
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#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1
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#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2
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#endif
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#endif /* __BOARDS_ARM_STM32_OMNIBUSF4_INCLUDE_BOARD_H */
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