543 lines
18 KiB
Plaintext
543 lines
18 KiB
Plaintext
README
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^^^^^^
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README for NuttX port to the Embedded Artists LPCXpresso LPC1115 board
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featuring the NXP LPC1115 MCU.
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Contents
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^^^^^^^^
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LCPXpresso LPC1115 Board
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Code Red IDE
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Using OpenOCD
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LEDs
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LPCXpresso Configuration Options
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Configurations
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LCPXpresso LPC1115 Board
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^^^^^^^^^^^^^^^^^^^^^^^^
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Pin Description Connector
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-------------------------------- ---------
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P0[0]/RD1/TXD3/SDA1 J6-9
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P0[1]/TD1/RXD3/SCL J6-10
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P0[2]/TXD0/AD0[7] J6-21
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P0[3]/RXD0/AD0[6] J6-22
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P0[4]/I2SRX-CLK/RD2/CAP2.0 J6-38
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P0[5]/I2SRX-WS/TD2/CAP2.1 J6-39
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P0[6]/I2SRX_SDA/SSEL1/MAT2[0] J6-8
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P0[7]/I2STX_CLK/SCK1/MAT2[1] J6-7
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P0[8]/I2STX_WS/MISO1/MAT2[2] J6-6
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P0[9]/I2STX_SDA/MOSI1/MAT2[3] J6-5
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P0[10] J6-40
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P0[11] J6-41
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P1[0]/ENET-TXD0 J6-34?
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P1[1]/ENET_TXD1 J6-35?
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P1[4]/ENET_TX_EN
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P1[8]/ENET_CRS
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P1[9]/ENET_RXD0
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P1[10]/ENET_RXD1
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P2[0]/PWM1.1/TXD1
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P2[1]/PWM1.2/RXD1 J6-43
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P2[2]/PWM1.3/CTS1/TRACEDATA[3] J6-44
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P2[3]/PWM1.4/DCD1/TRACEDATA[2] J6-45
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P2[4]/PWM1.5/DSR1/TRACEDATA[1] J6-46
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P2[5]/PWM1[6]/DTR1/TRACEDATA[0] J6-47
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P2[6]/PCAP1[0]/RI1/TRACECLK J6-48
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P2[7]/RD2/RTS1 J6-49
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P2[8]/TD2/TXD2 J6-50
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P2[9]/USB_CONNECT/RXD2 PAD19
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P2[10]/EINT0/NMI J6-51
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P3[25]/MAT0.0/PWM1.2 PAD13
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P3[26]/STCLK/MAT0.1/PWM1.3 PAD14
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Code Red IDE
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^^^^^^^^^^^^
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NuttX is built using command-line make. It can be used with an IDE, but some
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effort will be required to create the project.
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Makefile Build
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--------------
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Under Linux Eclipse, it is pretty easy to set up an "empty makefile project" and
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simply use the NuttX makefile to build the system. That is almost for free
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under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty
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makefile project in order to work with Windows (Google for "Eclipse Cygwin" -
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there is a lot of help on the internet).
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Native Build
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------------
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Here are a few tips before you start that effort:
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1) Select the toolchain that you will be using in your .config file
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2) Start the NuttX build at least one time from the Cygwin command line
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before trying to create your project. This is necessary to create
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certain auto-generated files and directories that will be needed.
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3) Set up include pathes: You will need include/, arch/arm/src/lpc11xx,
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arch/arm/src/common, arch/arm/src/armv7-m, and sched/.
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4) All assembly files need to have the definition option -D __ASSEMBLY__
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on the command line.
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Startup files will probably cause you some headaches. The NuttX startup file
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is arch/arm/src/lpc11x/lpc11_vectors.S.
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Using Code Red GNU Tools from Cygwin
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------------------------------------
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Under Cygwin, the Code Red command line tools (e.g., arm-non-eabi-gcc) cannot
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be executed because they only have execute privileges for Administrators. I
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worked around this by:
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Opening a native Cygwin RXVT as Administrator (Right click, "Run as administrator"),
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then executing 'chmod 755 *.exe' in the following directories:
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/cygdrive/c/nxp/lpcxpreeso_3.6/bin, and
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/cygdrive/c/nxp/lpcxpreeso_3.6/Tools/bin
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Command Line Flash Programming
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------------------------------
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During the port development was used a STLink-v2 SWD programmer with OpenOCD to
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write the firmware in the flash and GDB to debug NuttX initialization.
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If using LPCLink as your debug connection, first of all boot the LPC-Link using
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the script:
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bin\Scripts\bootLPCXpresso type
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where type = winusb for Windows XP, or type = hid for Windows Vista / 7.
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Now run the flash programming utility with the following options
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flash_utility wire -ptarget -flash-load[-exec]=filename [-load-base=base_address]
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Where flash_utility is one of:
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crt_emu_lpc11_13 (for LPC11xx or LPC13xx parts)
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crt_emu_cm3_nxp (for LPC11xx parts)
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crt_emu_a7_nxp (for LPC21/22/23/24 parts)
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crt_emu_a9_nxp (for LPC31/32 and LPC29xx parts)
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crt_emu_cm3_lmi (for TI Stellaris parts)
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wire is one of:
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(empty) (for Red Probe+, Red Probe, RDB1768v1, or TI Stellaris evaluation boards)
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-wire=hid (for RDB1768v2 without upgraded firmware)
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-wire=winusb (for RDB1768v2 with upgraded firmware)
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-wire=winusb (for LPC-Link on Windows XP)
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-wire=hid (for LPC-Link on Windows Vista/ Windows 7)
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target is the target chip name. For example LPC1343, LPC1114/301, LPC1115 etc.
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filename is the file to flash program. It may be an executable (axf) or a binary
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(bin) file. If using a binary file, the base_address must be specified.
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base_address is the base load address when flash programming a binary file. It
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should be specified as a hex value with a leading 0x.
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Note:
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- flash-load will leave the processor in a stopped state
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- flash-load-exec will start execution of application as soon as download has
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completed.
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Examples
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To load the executable file app.axf and start it executing on an LPC1158
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target using Red Probe, use the following command line:
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crt_emu_cm3_nxp -pLPC1158 -flash-load-exec=app.axf
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To load the binary file binary.bin to address 0x1000 to an LPC1343 target
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using LPC-Link on Windows XP, use the following command line:
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crt_emu_lpc11_13_nxp -wire=hid -pLPC1343 -flash-load=binary.bin -load-base=0x1000
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tools/flash.sh
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--------------
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All of the above steps are automated in the bash script flash.sh that can
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be found in the configs/lpcxpresso/tools directory.
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Using OpenOCD
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^^^^^^^^^^^^^
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https://acassis.wordpress.com/2015/03/29/using-openocd-to-program-the-lpc1115-lpcxpresso-board/
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Using OpenOCD to program the LPC1115 LPCXpresso board
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March 29, 2015 by acassis
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Unfortunately NXP uses a built-in programmer in the LPCXpresso board
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called LPCLink that is not supported by OpenOCD and there is not (AFAIK)
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an option to replace its firmware.
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Then I decided to cut the board to separate the “LPCXpresso LPC1115 REV A”
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from the LPCLink programmer.
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So I used a simple and low cost STLink-v2 programmer board that is
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supported by OpenOCD. In order to use OpenOCD to reprogram the LPC1115
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board we need to connect four wires from STLink-v2 to LPC1115 board:
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STLink-v2 | LPC1115 Board
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------------------------------
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GND GND
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3V3 3V3
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IO AD4
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CLK P0.10
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Also we need to instruct OpenOCD to use SWD protocol. You can do it
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creating the following config openocd.cfg file:
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# LPC1115 LPCXpresso Target
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# Using stlink as SWD programmer
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source [find interface/stlink-v2.cfg]
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# SWD as transport
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transport select hla_swd
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# Use LPC1115 target
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set WORKAREASIZE 0x4000
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source [find target/lpc11xx.cfg]
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Now execute OpenOCD using the created config file:
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$ sudo openocd -f openocd.cfg
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Open On-Chip Debugger 0.9.0-dev-00251-g1fa4c72 (2015-01-28-20:08)
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Licensed under GNU GPL v2
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For bug reports, read
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http://openocd.sourceforge.net/doc/doxygen/bugs.html
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Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
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adapter speed: 10 kHz
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adapter_nsrst_delay: 200
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Info : Unable to match requested speed 10 kHz, using 5 kHz
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Info : Unable to match requested speed 10 kHz, using 5 kHz
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Info : clock speed 5 kHz
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Info : STLINK v2 JTAG v17 API v2 SWIM v4 VID 0x0483 PID 0x3748
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Info : using stlink api v2
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Info : Target voltage: 3.137636
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Info : lpc11xx.cpu: hardware has 4 breakpoints, 2 watchpoints
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Connect to OpenOCD server:
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$ telnet 127.0.0.1 4444
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Reset the CPU and flash the lpc1115_blink.bin file:
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> reset halt
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target state: halted
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target halted due to debug-request, current mode: Thread
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xPSR: 0xc1000000 pc: 0x1fff0040 msp: 0x10000ffc
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> flash probe 0
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flash 'lpc2000' found at 0x00000000
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> flash write_image erase blink_lpc1115.bin 0x00000000
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auto erase enabled
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target state: halted
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target halted due to breakpoint, current mode: Thread
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xPSR: 0x01000000 pc: 0x10000108 msp: 0x100001b8
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Verification will fail since checksum in image (0x00000000) to be written to flash is different from calculated vector checksum (0xefffebe9).
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To remove this warning modify build tools on developer PC to inject correct LPC vector checksum.
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wrote 4096 bytes from file blink_lpc1115.bin in 0.592621s (6.750 KiB/s)
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> reset run
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The checksum warning message could be removed if you add the checksum to
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binary, read this post:
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http://sigalrm.blogspot.com.br/2011/10/cortex-m3-exception-vector-checksum.html.
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The blink LED sample I got from Frank Duignan’s page:
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http://eleceng.dit.ie/frank/arm/BareMetalLPC1114/index.html
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Edit Makefile and configure LIBSPEC to point out to the right path:
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LIBSPEC=-L /usr/lib/gcc/arm-none-eabi/4.8/armv6-m
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$ make
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To generate the final binary I used objcopy:
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$ arm-none-eabi-objcopy -O binary main.elf blink_lpc1115.bin
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https://acassis.wordpress.com/2015/05/22/using-openocd-and-gdb-to-debug-my-nuttx-port-to-lpc11xx/
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Using OpenOCD and gdb to debug my NuttX port to LPC11xx
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May 22, 2015 by acassis
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I’m porting NuttX to LPC11xx (using the LPCXpresso LPC1115 board) and
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these are the steps I used to get OpenOCD and GDB working to debug my firmware:
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The openocd.cfg to use with STLink-v2 SWD programmer:
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# LPC1115 LPCXpresso Target
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# Using stlink as SWD programmer
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source [find interface/stlink-v2.cfg]
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# SWD as transport
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transport select hla_swd
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# Use LPC1115 target
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set WORKAREASIZE 0x4000
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source [find target/lpc11xx.cfg]
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You need to execute “reset halt” from OpenOCD telnet server to get
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“monitor reset halt” working on gdb:
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$ telnet 127.0.0.1 4444Trying 127.0.0.1...
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Connected to 127.0.0.1.
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Escape character is '^]'.
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Open On-Chip Debugger
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> reset halt
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target state: halted
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target halted due to debug-request, current mode: Thread
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xPSR: 0xc1000000 pc: 0x1fff0040 msp: 0x10000ffc
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> exit
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Now execute the command arm-none-eabi-gdb (from Debian/Ubuntu package
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“gdb-arm-none-eabi”) passing the nuttx ELF file:
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$ arm-none-eabi-gdb nuttx
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GNU gdb (7.7.1+dfsg-1+6) 7.7.1
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Reading symbols from nuttx...done.
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(gdb) target remote localhost:3333
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Remote debugging using localhost:3333
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0x1fff0040 in ?? ()
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(gdb) monitor reset halt
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target state: halted
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target halted due to debug-request, current mode: Thread
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xPSR: 0xc1000000 pc: 0x1fff0040 msp: 0x10000ffc
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(gdb) load
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Loading section .vectors, size 0xc0 lma 0x0
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Loading section .text, size 0x9197 lma 0x410
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Loading section .ARM.exidx, size 0x8 lma 0x95a8
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Loading section .data, size 0x48 lma 0x95b0
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Start address 0x410, load size 37543
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Transfer rate: 9 KB/sec, 6257 bytes/write.
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(gdb) b __start
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Breakpoint 1 at 0x410: file chip/lpc11_start.c, line 109.
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(gdb) step
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Note: automatically using hardware breakpoints for read-only addresses.
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Breakpoint 1, __start () at chip/lpc11_start.c:109
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109 {
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(gdb)
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115 lpc11_clockconfig();
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(gdb)
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lpc11_clockconfig () at chip/lpc11_clockconfig.c:93
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93 putreg32(SYSCON_SYSPLLCLKSEL_IRCOSC, LPC11_SYSCON_SYSPLLCLKSEL);
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(gdb)
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96 putreg32((SYSCON_SYSPLLCTRL_MSEL_DIV(4) | SYSCON_SYSPLLCTRL_PSEL_DIV2), LPC11_SYSCON_SYSPLLCTRL);
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(gdb) p /x *0x40048008 <--- this is the LPC11_SYSCON_SYSPLLCTRL register address
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$2 = 0x23
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(gdb)
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You can use breakpoints, steps and many other GDB features.
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That is it!
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LEDs
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^^^^
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If CONFIG_ARCH_LEDS is defined, then support for the LPCXpresso LEDs will be
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included in the build. See:
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- configs/lpcxpresso-lpc1115/include/board.h - Defines LED constants, types and
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prototypes the LED interface functions.
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- configs/lpcxpresso-lpc1115/src/lpcxpresso-lpc1115.h - GPIO settings for the LEDs.
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- configs/lpcxpresso-lpc1115/src/up_leds.c - LED control logic.
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The LPCXpresso LPC1115 has a single LEDs. Usage this single LED by NuttX
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is as follows:
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- The LED is not illuminated until the LPCXpresso completes initialization.
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If the LED is stuck in the OFF state, this means that the LPCXpresso did not
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complete initializeation.
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- Each time the OS enters an interrupt (or a signal) it will turn the LED OFF and
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restores its previous stated upon return from the interrupt (or signal).
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The normal state, after initialization will be a dull glow. The brightness of
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the glow will be inversely related to the proportion of time spent within interrupt
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handling logic. The glow may decrease in brightness when the system is very
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busy handling device interrupts and increase in brightness as the system becomes
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idle.
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Stuck in the OFF state suggests that that the system never completed
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initialization; Stuck in the ON state would indicated that the system
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intialialized, but is not takint interrupts.
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- If a fatal assertion or a fatal unhandled exception occurs, the LED will flash
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strongly as a slow, 2Hz rate.
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LPCXpresso Configuration Options
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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General Architecture Settings:
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CONFIG_ARCH - Identifies the arch/ subdirectory. This should
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be set to:
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CONFIG_ARCH=arm
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CONFIG_ARCH_family - For use in C code:
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CONFIG_ARCH_ARM=y
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CONFIG_ARCH_architecture - For use in C code:
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CONFIG_ARCH_CORTEXM0=y
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CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
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CONFIG_ARCH_CHIP=lpc11xx
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CONFIG_ARCH_CHIP_name - For use in C code to identify the exact
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chip:
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CONFIG_ARCH_CHIP_LPC1115=y
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CONFIG_ARCH_BOARD - Identifies the configs subdirectory and
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hence, the board that supports the particular chip or SoC.
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CONFIG_ARCH_BOARD=lpcxpresso-lpc1115
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CONFIG_ARCH_BOARD_name - For use in C code
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CONFIG_ARCH_BOARD_LPCEXPRESSO=y
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CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation
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of delay loops
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CONFIG_ENDIAN_BIG - define if big endian (default is little
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endian)
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CONFIG_RAM_SIZE - Describes the installed DRAM (CPU SRAM in this case):
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CONFIG_RAM_SIZE=(8*1024) (8Kb)
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There is an additional 32Kb of SRAM in AHB SRAM banks 0 and 1.
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CONFIG_RAM_START - The start address of installed DRAM
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CONFIG_RAM_START=0x10000000
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CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that
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have LEDs
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CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
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stack. If defined, this symbol is the size of the interrupt
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stack in bytes. If not defined, the user task stacks will be
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used during interrupt handling.
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CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
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CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture.
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CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that
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cause a 100 second delay during boot-up. This 100 second delay
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serves no purpose other than it allows you to calibratre
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CONFIG_ARCH_LOOPSPERMSEC. You simply use a stop watch to measure
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the 100 second delay then adjust CONFIG_ARCH_LOOPSPERMSEC until
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the delay actually is 100 seconds.
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Individual subsystems can be enabled:
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CONFIG_LPC11_MAINOSC=y
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CONFIG_LPC11_PLL0=y
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CONFIG_LPC11_UART0=y
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CONFIG_LPC11_CAN1=n
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CONFIG_LPC11_SPI=n
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CONFIG_LPC11_SSP0=n
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CONFIG_LPC11_SSP1=n
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CONFIG_LPC11_I2C0=n
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CONFIG_LPC11_I2S=n
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CONFIG_LPC11_TMR0=n
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CONFIG_LPC11_TMR1=n
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CONFIG_LPC11_PWM0=n
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CONFIG_LPC11_ADC=n
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CONFIG_LPC11_FLASH=n
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LPC11xx specific device driver settings
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CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the
|
||
console and ttys0 (default is the UART0).
|
||
CONFIG_UARTn_RXBUFSIZE - Characters are buffered as received.
|
||
This specific the size of the receive buffer
|
||
CONFIG_UARTn_TXBUFSIZE - Characters are buffered before
|
||
being sent. This specific the size of the transmit buffer
|
||
CONFIG_UARTn_BAUD - The configure BAUD of the UART. Must be
|
||
CONFIG_UARTn_BITS - The number of bits. Must be either 7 or 8.
|
||
CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
|
||
CONFIG_UARTn_2STOP - Two stop bits
|
||
|
||
LPC11xx specific CAN device driver settings. These settings all
|
||
require CONFIG_CAN:
|
||
|
||
CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID. Default
|
||
Standard 11-bit IDs.
|
||
CONFIG_LPC11_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_LPC11_CAN1
|
||
is defined.
|
||
CONFIG_LPC11_CAN1_DIVISOR - CAN1 is clocked at CCLK divided by this
|
||
number. (the CCLK frequency is divided by this number to get the CAN
|
||
clock). Options = {1,2,4,6}. Default: 4.
|
||
CONFIG_LPC11_CAN_TSEG1 - The number of CAN time quanta in segment 1. Default: 6
|
||
|
||
Configurations
|
||
^^^^^^^^^^^^^^
|
||
|
||
Each LPCXpresso configuration is maintained in a sub-directory and can be
|
||
selected as follow:
|
||
|
||
tools/configure.sh lpcxpresso-lpc1115/<subdir>
|
||
|
||
Where <subdir> is one of the following:
|
||
|
||
nsh:
|
||
---
|
||
|
||
Configures the NuttShell (nsh) located at apps/examples/nsh. The
|
||
Configuration enables both the serial and telnet NSH interfaces.
|
||
|
||
NOTES:
|
||
|
||
1. This configuration uses the mconf-based configuration tool. To
|
||
change this configurations using that tool, you should:
|
||
|
||
a. Build and install the kconfig-mconf tool. See nuttx/README.txt
|
||
see additional README.txt files in the NuttX tools repository.
|
||
|
||
b. Execute 'make menuconfig' in nuttx/ in order to start the
|
||
reconfiguration process.
|
||
|
||
2. This configuration has been used for testing the microSD card.
|
||
This support is, however, disabled in the base configuration.
|
||
|
||
At last attempt, the SPI-based mircroSD does not work at
|
||
higher fequencies. Setting the SPI frequency to 400000
|
||
removes the problem. There must be some more optimal
|
||
value that could be determined with additional experimetnation.
|
||
|
||
Jumpers: J55 must be set to provide chip select PIO1_11 signal as
|
||
the SD slot chip select.
|