nuttx/arch/risc-v/include
Huang Qi 93d75129de riscv: Add Vector CSRs to csr.h
The CSR register definitions from RVV 1.0 spec: https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-registers

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2024-04-19 00:31:07 +08:00
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bl602
bl808
c906
esp32c3
esp32c3-legacy
esp32c6
esp32h2
fe310
hpm6000
hpm6750
jh7110
k210
k230
litex
mpfs
qemu-rv
rv32m1
thead
.gitignore
arch.h
barriers.h
csr.h riscv: Add Vector CSRs to csr.h 2024-04-19 00:31:07 +08:00
elf.h
inttypes.h
irq.h
limits.h
mode.h
setjmp.h
spinlock.h
stdarg.h
syscall.h
types.h