Stuart Ianna ee84ea3875 arch/risc-v/litex/litex_gpio: Fix ISR dispatch when using higher GPIO indexes. ... Previously, GPIO interrupts were not correctly mapped to the peripheral base register responsible for the interrupt. Change the IRQ number calculation so the interrupts work correctly on all GPIO peripheral bases.		2023-10-25 15:42:25 +08:00
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bl602
c906
esp32c3
esp32c6
espressif	arch/risc-v/espressif: Add full GPIO support	2023-06-24 13:11:45 +08:00
fe310
hpm6750
jh7110	arch/risc-v: Add support for StarFive JH7110 SoC	2023-08-03 22:55:55 -07:00
k210
litex	arch/risc-v/litex/litex_gpio: Fix ISR dispatch when using higher GPIO indexes.	2023-10-25 15:42:25 +08:00
mpfs
qemu-rv
rv32m1
.gitignore
arch.h
barriers.h	riscv/barrier: Define more granular memory barriers	2023-06-14 16:14:57 -03:00
csr.h
elf.h
inttypes.h
irq.h	riscv/lazyfpu: Add option to disable lazy FPU	2023-07-31 07:48:53 -07:00
limits.h
mode.h
setjmp.h
spinlock.h
stdarg.h
syscall.h	arch/risc-v: change up_saveusercontext to assembly code	2023-04-27 17:34:30 +08:00
types.h