398 lines
17 KiB
C
398 lines
17 KiB
C
/****************************************************************************
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* arch/mips/include/pic32mz/cp0.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __ARCH_MIPS_INCLUDE_PIC32MZ_CP0_H
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#define __ARCH_MIPS_INCLUDE_PIC32MZ_CP0_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <arch/mips32/cp0.h>
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/****************************************************************************
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* Pre-Processor Definitions
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****************************************************************************/
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/* CP0 Register Addresses ***************************************************/
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#ifdef __ASSEMBLY__
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# define PIC32MZ_CP0_HWRENA $7,0 /* Enables access via RDHWR hardware registers */
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# define PIC32MZ_CP0_BADVADDR $8,0 /* Address of most recent exception */
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# define PIC32MZ_CP0_COUNT $9,0 /* Processor cycle count */
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# define PIC32MZ_CP0_COMPARE $11,0 /* Timer interrupt control */
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# define PIC32MZ_CP0_STATUS $12,0 /* Processor status and control */
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# define PIC32MZ_CP0_INTCTL $12,1 /* Interrupt system status and control */
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# define PIC32MZ_CP0_SRSCTL $12,2 /* Shadow register set status and control */
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# define PIC32MZ_CP0_SRSMAP $12,3 /* Maps from vectored interrupt to a shadow set */
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# define PIC32MZ_CP0_CAUSE $13,0 /* Cause of last general exception */
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# define PIC32MZ_CP0_EPC $14,0 /* Program counter at last exception */
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# define PIC32MZ_CP0_PRID $15,0 /* Processor identification and revision */
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# define PIC32MZ_CP0_EBASE $15,1 /* Exception vector base register */
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# define PIC32MZ_CP0_CONFIG $16,0 /* Configuration register */
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# define PIC32MZ_CP0_CONFIG1 $16,1 /* Configuration register 1 */
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# define PIC32MZ_CP0_CONFIG2 $16,2 /* Configuration register 3 */
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# define PIC32MZ_CP0_CONFIG3 $16,3 /* Configuration register 3 */
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# define PIC32MZ_CP0_DEBUG $23,3 /* Debug control and exception status */
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# define PIC32MZ_CP0_DEPC $24,3 /* Program counter at last debug exception */
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# define PIC32MZ_CP0_ERREPC $30,3 /* Program counter at last error */
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# define PIC32MZ_CP0_DESAVE $31,3 /* Debug handler scratchpad register */
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#endif
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/* CP0 Registers ************************************************************/
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/* Register Number: 0-6: Reserved
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* Compliance Level: Required for TLB-based MMU; Optional otherwise.
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*/
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/* Register Number: 7 Sel: 0 Name: HWREna
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* Function: Enables access via the RDHWR instruction to selected hardware
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* registers in non-privileged mode.
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* Compliance Level: (Reserved for future extensions)
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*/
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#define CP0_HWRENA_SHIFT (0) /* Bits 0-3: Enable access to a hardware resource */
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#define CP0_HWRENA_MASK (15 << CP0_HWRENA_SHIFT)
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# define CP0_HWRENA_BIT0 (1 << CP0_HWRENA_SHIFT)
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# define CP0_HWRENA_BIT1 (2 << CP0_HWRENA_SHIFT)
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# define CP0_HWRENA_BIT2 (4 << CP0_HWRENA_SHIFT)
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# define CP0_HWRENA_BIT3 (8 << CP0_HWRENA_SHIFT)
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/* Register Number: 8 Sel: 0 Name: BadVAddr
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* Function: Reports the address for the most recent address-related
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* exception
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* Compliance Level: Required.
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*
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* See arch/mips/include/mips32/cp0.h
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*
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* Register Number: 9 Sel: 0 Name: Count
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* Function: Processor cycle count
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* Compliance Level: Required.
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*
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* See arch/mips/include/mips32/cp0.h
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*
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* Register Number: 10 Reserved.
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* Compliance Level: Required for TLB-based MMU; Optional otherwise.
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*
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* Register Number: 11 Sel: 0 Name: Compare
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* Function: Timer interrupt control
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* Compliance Level: Required.
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*
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* See arch/mips/include/mips32/cp0.h
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*/
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/* Register Number: 12 Sel: 0 Name: Status
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* Function: Processor status and control
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* Compliance Level: Required.
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*
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* See arch/mips/include/mips32/cp0.h
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* NOTES:
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* 1. The following are reserved bits in the PIC32:
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* CP0_STATUS_UX Bit 5: Enables 64-bit user address space (Not MIPS32)
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* CP0_STATUS_SX Bit 6: Enables 64-bit supervisor address space (Not MIPS32)
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* CP0_STATUS_KX Bit 7: Enables 64-bit kernel address space (Not MIPS32)
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* CP0_STATUS_IMPL Bits 16-17: Implementation dependent
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* CP0_STATUS_TS Bit 21: TLB detected match on multiple entries
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* CP0_STATUS_PX Bit 23: Enables 64-bit operations (Not MIPS32)
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* CP0_STATUS_MX Bit 24: Enables MDMX<4D> (Not MIPS32)
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*/
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#undef CP0_STATUS_UX
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#undef CP0_STATUS_SX
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#undef CP0_STATUS_KX
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#undef CP0_STATUS_IMPL
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#undef CP0_STATUS_IMPL_SHIFT
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#undef CP0_STATUS_IMPL_MASK
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#undef CP0_STATUS_TS
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#undef CP0_STATUS_PX
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#undef CP0_STATUS_MX
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/* 2. The following field is of a different width. Apparently, it
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* excludes the software interrupt bits.
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*
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* CP0_STATUS_IM Bits 8-15: Interrupt Mask
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* Vs.
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* CP0_STATUS_IPL Bits 10-15: Interrupt priority level
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* Bitss 8-9 reserved
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*/
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#define CP0_STATUS_IPL_SHIFT (10) /* Bits 10-15: Interrupt priority level */
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#define CP0_STATUS_IPL_MASK (0x3f << CP0_STATUS_IPL_SHIFT)
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/* 3. Supervisor mode not supported
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* CP0_STATUS_KSU Bits 3-4: Operating mode (with supervisor mode)
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*/
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#undef CP0_STATUS_KSU_SHIFT
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#undef CP0_STATUS_KSU_MASK
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#undef CP0_STATUS_KSU_KERNEL
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#undef CP0_STATUS_KSU_SUPER
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#undef CP0_STATUS_KSU_USER
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/* Register Number: 12 Sel: 1 Name: IntCtl */
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#define CP0_INTCTL_VS_SHIFT (5) /* Bits 5-9: Vector spacing bits */
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#define CP0_INTCTL_VS_MASK (0x1f << CP0_INTCTL_VS_SHIFT)
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# define CP0_INTCTL_VS_0BYTES (0x00 << CP0_INTCTL_VS_SHIFT)
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# define CP0_INTCTL_VS_32BYTES (0x01 << CP0_INTCTL_VS_SHIFT)
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# define CP0_INTCTL_VS_64BYTES (0x02 << CP0_INTCTL_VS_SHIFT)
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# define CP0_INTCTL_VS_128BYTES (0x04 << CP0_INTCTL_VS_SHIFT)
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# define CP0_INTCTL_VS_256BYTES (0x08 << CP0_INTCTL_VS_SHIFT)
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# define CP0_INTCTL_VS_512BYTES (0x10 << CP0_INTCTL_VS_SHIFT)
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/* Register Number: 12 Sel: 2 Name: SRSCtl */
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#define CP0_SRSCTL_CSS_SHIFT (0) /* Bits 0-3: Current shadow bit set */
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#define CP0_SRSCTL_CSS_MASK (15 << CP0_SRSCTL_CSS_SHIFT)
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#define CP0_SRSCTL_PSS_SHIFT (6) /* Bits 6-9: Previous shadow set */
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#define CP0_SRSCTL_PSS_MASK (15 << CP0_SRSCTL_PSS_SHIFT)
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#define CP0_SRSCTL_ESS_SHIFT (12) /* Bits 12-15: Exception shadow sets */
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#define CP0_SRSCTL_ESS_MASK (15 << CP0_SRSCTL_ESS_SHIFT)
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#define CP0_SRSCTL_EICSS_SHIFT (18) /* Bits 18-21: External interrupt controller shadow sets */
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#define CP0_SRSCTL_EICSS_MASK (15 << CP0_SRSCTL_EICSS_SHIFT)
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#define CP0_SRSCTL_HSS_SHIFT (26) /* Bits 26-29: High shadow sets */
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#define CP0_SRSCTL_HSS_MASK (15 << CP0_SRSCTL_HSS_SHIFT)
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# define CP0_SRSCTL_HSS_1SET (0 << CP0_SRSCTL_HSS_SHIFT) /* One shadow set (normal GPR set) */
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# define CP0_SRSCTL_HSS_2SETS (1 << CP0_SRSCTL_HSS_SHIFT) /* Two shadow sets */
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# define CP0_SRSCTL_HSS_4SETS (3 << CP0_SRSCTL_HSS_SHIFT) /* Four shadow sets */
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/* Register Number: 12 Sel: 3 Name: SRSMap */
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#define CP0_SRSMAP_SSV0_SHIFT (0) /* Bits 0-3: Shadow set vector 0 */
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#define CP0_SRSMAP_SSV0_MASK (15 << CP0_SRSMAP_SSV0_SHIFT)
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#define CP0_SRSMAP_SSV1_SHIFT (4) /* Bits 4-7: Shadow set vector 1 */
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#define CP0_SRSMAP_SSV1_MASK (15 << CP0_SRSMAP_SSV1_SHIFT)
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#define CP0_SRSMAP_SSV2_SHIFT (8) /* Bits 8-11: Shadow set vector 2 */
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#define CP0_SRSMAP_SSV2_MASK (15 << CP0_SRSMAP_SSV2_SHIFT)
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#define CP0_SRSMAP_SSV3_SHIFT (12) /* Bits 12-15: Shadow set vector 3 */
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#define CP0_SRSMAP_SSV3_MASK (15 << CP0_SRSMAP_SSV3_SHIFT)
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#define CP0_SRSMAP_SSV4_SHIFT (16) /* Bits 16-19: Shadow set vector 4 */
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#define CP0_SRSMAP_SSV4_MASK (15 << CP0_SRSMAP_SSV4_SHIFT)
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#define CP0_SRSMAP_SSV5_SHIFT (20) /* Bits 20-23: Shadow set vector 5 */
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#define CP0_SRSMAP_SSV5_MASK (15 << CP0_SRSMAP_SSV5_SHIFT)
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#define CP0_SRSMAP_SSV6_SHIFT (24) /* Bits 24-27: Shadow set vector 6 */
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#define CP0_SRSMAP_SSV6_MASK (15 << CP0_SRSMAP_SSV6_SHIFT)
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#define CP0_SRSMAP_SSV7_SHIFT (28) /* Bits 28-31: Shadow set vector 7 */
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#define CP0_SRSMAP_SSV7_MASK (15 << CP0_SRSMAP_SSV7_SHIFT)
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/* Register Number: 13 Sel: 0 Name: Cause
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* Function: Cause of last general exception
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* Compliance Level: Required.
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*
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* See arch/mips/include/mips32/cp0.h
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* NOTES: The following bits are added in the PIC32:
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*/
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#define CP0_CAUSE_R (1 << 26) /* Bit 26: R bit */
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#define CP0_CAUSE_DC (1 << 27) /* Bit 27: Disable count */
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#define CP0_CAUSE_TI (1 << 30) /* Bit 30: Timer interrupt bit *.
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/* Register Number: 14 Sel: 0 Name: EPC
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* Function: Program counter at last exception
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* Compliance Level: Required.
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*
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* See arch/mips/include/mips32/cp0.h
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*/
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/* Register Number: 15 Sel: 0 Name: PRId
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* Function: Processor identification and revision
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* Compliance Level: Required.
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*
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* See arch/mips/include/mips32/cp0.h
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* NOTE: Slightly different bit interpretations of some fields:
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*/
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#define CP0_PRID_PATCH_SHIFT (5) /* Bits 0-1: Patch level */
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#define CP0_PRID_PATCH_MASK (3 << CP0_PRID_PATCH_SHIFT)
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#define CP0_PRID_MINOR_SHIFT (2) /* Bits 2-4: Minor revision number */
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#define CP0_PRID_MINOR_MASK (7 << CP0_PRID_MINOR_SHIFT)
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#define CP0_PRID_MAJOR_SHIFT (5) /* Bits 5-7: Major revision number */
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#define CP0_PRID_MAJOR_MASK (7 << CP0_PRID_MAJOR_SHIFT)
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#undef CP0_PRID_OPTIONS_SHIFT
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#undef CP0_PRID_OPTIONS_MASK
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/* Register Number: 15 Sel: 1 Name: EBASE */
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#define CP_EBASE_CPUNUM_SHIFT (0) /* Bits 0-9: CPU number */
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#define CP_EBASE_CPUNUM_MASK (0x3ff << CP_EBASE_CPUNUM_SHIFT)
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#define CP_EBASE_SHIFT (12) /* Bits 30-31=10, Bits 12-29: Exception base */
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#define CP_EBASE_MASK (0x3ffff << CP_EBASE_SHIFT)
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/* Register Number: 16 Sel: 0 Name: Config
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* Function: Configuration register
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* Compliance Level: Required.
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*
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* See arch/mips/include/mips32/cp0.h
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* 1. PIC32MZ is always little-endian.
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* 2. Implementation specific bits defined.
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*/
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#undef CP0_CONFIG_IMPL_SHIFT
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#undef CP0_CONFIG_IMPL_MASK
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#define CP0_CONFIG_K23_SHIFT (0) /* Bits 28-30: KSEG2 and KSEG3 cacheability */
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#define CP0_CONFIG_K23_MASK (7 << CP0_CONFIG_K23_SHIFT)
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# define CP0_CONFIG_K23_UNCACHED (2 << CP0_CONFIG_K23_SHIFT)
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# define CP0_CONFIG_K23_CACHEABLE (3 << CP0_CONFIG_K23_SHIFT)
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#define CP0_CONFIG_KU_SHIFT (0) /* Bits 0-2: KUSEG and USEG cacheability */
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#define CP0_CONFIG_KU_MASK (7 << CP0_CONFIG_KU_SHIFT)
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# define CP0_CONFIG_KU_UNCACHED (2 << CP0_CONFIG_KU_SHIFT)
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# define CP0_CONFIG_KU_CACHEABLE (3 << CP0_CONFIG_KU_SHIFT)
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#define CP0_CONFIG_UDI (1 << 22) /* Bit 22: User defined bit */
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#define CP0_CONFIG_SB (1 << 21) /* Bit 32: Simple BE bus mode bit */
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#define CP0_CONFIG_MDU (1 << 20) /* Multipley/Divide unit bit */
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#define CP0_CONFIG_DS (1 << 16) /* Dual SRAM bit */
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/* Register Number: 16 Sel: 1 Name: Config1
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* Function: Configuration register 1
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* Compliance Level: Required.
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*
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* See arch/mips/include/mips32/cp0.h
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*
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* Register Number: 16 Sel: 2 Name: Config2
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* Function: Configuration register 2
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* Compliance Level: Optional.
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*
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* See arch/mips/include/mips32/cp0.h
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*/
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#undef CP0_CONFIG2_TBS_SHIFT
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#undef CP0_CONFIG2_TBS_MASK
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/* Register Number: 16 Sel: 3 Name: Config3
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* Function: Configuration register 3
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* Compliance Level: Optional.
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*
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* See arch/mips/include/mips32/cp0.h
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*/
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#define CP0_CONFIG3_SP (1 << 4) /* Bit 4: Support page bit */
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#define CP0_CONFIG3_VINT (1 << 5) /* Bit 5: Vector interrupt bit */
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#define CP0_CONFIG3_VEIC (1 << 6) /* Bit 6: External interrupt controller supported */
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/* Register Number: 17-22 Reserved
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* Compliance Level: Optional.
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*/
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/* Register Number: 23 Sel: 0 Name: Debug
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* Function: EJTAG Debug register
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* Compliance Level: Optional.
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*/
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#define CP0_DEBUG_DSS (1 << 0) /* Bit 0: Debug single-step exception */
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#define CP0_DEBUG_DBP (1 << 1) /* Bit 1: Debug software breakpoint exception */
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#define CP0_DEBUG_DDBL (1 << 2) /* Bit 2: Debug data break exception on load */
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#define CP0_DEBUG_DDBS (1 << 3) /* Bit 3: Debug data break exception on store */
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#define CP0_DEBUG_DIB (1 << 4) /* Bit 4: Debug instruction break exception */
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#define CP0_DEBUG_DINT (1 << 5) /* Bit 5: Debug interrupt exception */
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#define CP0_DEBUG_SST (1 << 8) /* Bit 6: Enable debug single step exception */
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#define CP0_DEBUG_NOSST (1 << 9) /* Bit 7: No single step feature available */
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#define CP0_DEBUG_DEXCCODE_SHIFT (10) /* Bits 10-14: Cause of latest exception in DEBUG mode */
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#define CP0_DEBUG_DEXCCODE_MASK (31 << CP0_DEBUG_DEXCCODE_SHIFT)
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#define CP0_DEBUG_VER_SHIFT (15) /* Bits 15-17: EJTAG version */
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#define CP0_DEBUG_VER_MASK (7 << CP0_DEBUG_VER_SHIFT)
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#define CP0_DEBUG_DDBLIMPR (1 << 18) /* Bit 18: Imprecise debug data break load instruction */
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#define CP0_DEBUG_DDBSIMPR (1 << 19) /* Bit 19: Imprecise debug data break store instruction */
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#define CP0_DEBUG_IEXI (1 << 20) /* Bit 20: Imprecise error exception inhibit */
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#define CP0_DEBUG_DBUSEP (1 << 21) /* Bit 21: Data access bus error exception pending */
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#define CP0_DEBUG_CACHEEP (1 << 22) /* Bit 22: Imprecise cache error exception is pending */
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#define CP0_DEBUG_MCHECKP (1 << 23) /* Bit 23: Imprecise machine check exception is pending */
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#define CP0_DEBUG_IBUSEP (1 << 24) /* Bit 24: Bus error exception pending */
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#define CP0_DEBUG_COUNTDM (1 << 25) /* Bit 25: Count register behavior (1=running) */
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#define CP0_DEBUG_HALT (1 << 26) /* Bit 26: Internal system bus clock stopped */
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#define CP0_DEBUG_DOZE (1 << 27) /* Bit 27: Processor in low power mode */
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#define CP0_DEBUG_LSNM (1 << 28) /* Bit 28: Load/store in DSEG goes to main memory */
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#define CP0_DEBUG_NODCR (1 << 29) /* Bit 29: No DSEG preset */
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#define CP0_DEBUG_DM (1 << 30) /* Bit 30: Processor is operating in DEBUG mode */
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#define CP0_DEBUG_DBD (1 << 31) /* Bit 31: Last debug exception occurred in a dely slot */
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/* Register Number: 23 Sel: ? Name: Debug2
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* Is this documented anywhere?
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*/
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/* Register Number: 24 Sel: 0 Name: DEPC
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* Function: Program counter at last EJTAG debug exception
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* Compliance Level: Optional.
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*
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* See arch/mips/include/mips32/cp0.h
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*
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* Register Number: 25-29 Reserved
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* Compliance Level: Recommended/Optional.
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*
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* Register Number: 30 Sel: 0 Name: ErrorEPC
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* Function: Program counter at last error
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* Compliance Level: Required.
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*
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* See arch/mips/include/mips32/cp0.h
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*
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* Register Number: 31 Sel: 0 Name: DeSAVE
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* Function: EJTAG debug exception save register
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* Compliance Level: Optional.
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*
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* See arch/mips/include/mips32/cp0.h
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*/
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/****************************************************************************
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* Inline Functions
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_MIPS_INCLUDE_PIC32MZ_CP0_H */
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