016bc47a63
Provide `up_copy_section` function that enables copying data using the data bus. If the memory destination address is accessible through the instruction bus, the data is copied using the correspondent address accessible through the data bus.
341 lines
9.1 KiB
Plaintext
341 lines
9.1 KiB
Plaintext
#
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# For a description of the syntax of this configuration file,
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# see the file kconfig-language.txt in the NuttX tools repository.
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#
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if ARCH_XTENSA
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choice
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prompt "XTENSA architecture selection"
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default ARCH_CHIP_ESP32
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config ARCH_CHIP_ESP32
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bool "Espressif ESP32"
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select ARCH_FAMILY_LX6
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select XTENSA_HAVE_INTERRUPTS
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select ARCH_HAVE_BOOTLOADER
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select ARCH_HAVE_FPU
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select ARCH_HAVE_MPU
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select ARCH_HAVE_MULTICPU
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select ARCH_HAVE_RESET
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select ARCH_HAVE_TESTSET
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select ARCH_HAVE_TEXT_HEAP
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select ARCH_VECNOTIRQ
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select LIBC_PREVENT_STRING_KERNEL
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select LIBC_ARCH_ATOMIC
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select LIBC_ARCH_MEMCPY if BUILD_FLAT
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select LIBC_ARCH_MEMCHR if BUILD_FLAT
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select LIBC_ARCH_MEMCMP if BUILD_FLAT
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select LIBC_ARCH_MEMMOVE if BUILD_FLAT
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select LIBC_ARCH_MEMSET if BUILD_FLAT
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select LIBC_ARCH_STRCHR if BUILD_FLAT
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select LIBC_ARCH_STRCMP if BUILD_FLAT
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select LIBC_ARCH_STRCPY if BUILD_FLAT
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select LIBC_ARCH_STRLCPY if BUILD_FLAT
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select LIBC_ARCH_STRNCPY if BUILD_FLAT
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select LIBC_ARCH_STRLEN if BUILD_FLAT
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select LIBC_ARCH_STRNLEN if BUILD_FLAT
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---help---
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The ESP32 is a dual-core system from Espressif with two Harvard
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architecture Xtensa LX6 CPUs. All embedded memory, external memory
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and peripherals are located on the data bus and/or the instruction
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bus of these CPUs. With some minor exceptions, the address mapping
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of two CPUs is symmetric, meaning they use the same addresses to
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access the same memory.
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The two CPUs are named "PRO_CPU" and "APP_CPU" (for "protocol" and
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"application"), however for most purposes the two CPUs are
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interchangeable.
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config ARCH_CHIP_ESP32S2
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bool "Espressif ESP32-S2"
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select ARCH_FAMILY_LX7
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select XTENSA_HAVE_INTERRUPTS
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select ARCH_HAVE_BOOTLOADER
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select ARCH_HAVE_RESET
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select ARCH_HAVE_TEXT_HEAP
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select ARCH_VECNOTIRQ
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select LIBC_ARCH_ATOMIC
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select LIBC_ARCH_MEMCPY
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select LIBC_ARCH_MEMCHR
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select LIBC_ARCH_MEMCMP
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select LIBC_ARCH_MEMMOVE
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select LIBC_ARCH_MEMSET
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select LIBC_ARCH_STRCHR
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select LIBC_ARCH_STRCMP
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select LIBC_ARCH_STRCPY
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select LIBC_ARCH_STRLCPY
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select LIBC_ARCH_STRNCPY
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select LIBC_ARCH_STRLEN
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select LIBC_ARCH_STRNLEN
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---help---
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ESP32-S2 is a truly secure, highly integrated, low-power, 2.4 GHz Wi-Fi
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Microcontroller SoC supporting Wi-Fi HT40 and having 43 GPIOs.
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Based on an Xtensa single-core 32-bit LX7 processor, it can be clocked
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at up to 240 MHz.
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config ARCH_CHIP_ESP32S3
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bool "Espressif ESP32-S3"
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select ARCH_FAMILY_LX7
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select XTENSA_HAVE_INTERRUPTS
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select ARCH_HAVE_BOOTLOADER if !ESPRESSIF_SIMPLE_BOOT
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select ARCH_HAVE_COPY_SECTION
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select ARCH_HAVE_FPU
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select ARCH_HAVE_MPU
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select ARCH_HAVE_MULTICPU
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select ARCH_HAVE_RESET
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select ARCH_HAVE_TEXT_HEAP
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select ARCH_HAVE_TEXT_HEAP_SEPARATE_DATA_ADDRESS
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select ARCH_HAVE_TEXT_HEAP_WORD_ALIGNED_READ
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select ARCH_HAVE_TESTSET
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select ARCH_VECNOTIRQ
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select LIBC_PREVENT_STRING_KERNEL
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select LIBC_ARCH_ATOMIC
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select LIBC_ARCH_MEMCPY if BUILD_FLAT
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select LIBC_ARCH_MEMCHR if BUILD_FLAT
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select LIBC_ARCH_MEMCMP if BUILD_FLAT
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select LIBC_ARCH_MEMMOVE if BUILD_FLAT
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select LIBC_ARCH_MEMSET if BUILD_FLAT
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select LIBC_ARCH_STRCHR if BUILD_FLAT
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select LIBC_ARCH_STRCMP if BUILD_FLAT
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select LIBC_ARCH_STRCPY if BUILD_FLAT
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select LIBC_ARCH_STRLCPY if BUILD_FLAT
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select LIBC_ARCH_STRNCPY if BUILD_FLAT
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select LIBC_ARCH_STRLEN if BUILD_FLAT
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select LIBC_ARCH_STRNLEN if BUILD_FLAT
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---help---
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ESP32-S3 is a dual-core Xtensa LX7 MCU, capable of running at 240 MHz.
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Apart from its 512 KB of internal SRAM, it also comes with integrated 2.4 GHz,
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802.11 b/g/n Wi-Fi and Bluetooth 5 (LE) connectivity that provides long-range
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support.
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config ARCH_CHIP_XTENSA_CUSTOM
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bool "Custom XTENSA chip"
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select ARCH_CHIP_CUSTOM
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---help---
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Select this option if there is no directory for the chip under arch/xtensa/src/.
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endchoice # XTENSA chip selection
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config XTENSA_HAVE_ICACHE
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bool
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default n
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config XTENSA_HAVE_DCACHE
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bool
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default n
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config XTENSA_HAVE_ICACHE_LOCK
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bool
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default n
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config XTENSA_HAVE_DCACHE_LOCK
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bool
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default n
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config XTENSA_HAVE_GENERAL_EXCEPTION_HOOKS
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bool
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default n
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config XTENSA_HAVE_WINDOW_EXCEPTION_HOOKS
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bool
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default n
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config XTENSA_ICACHE
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bool "Use I-Cache"
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default n
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depends on XTENSA_HAVE_ICACHE
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select ARCH_ICACHE
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---help---
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Enable Xtensa I-Cache
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config XTENSA_DCACHE
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bool "Use D-Cache"
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default n
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depends on XTENSA_HAVE_DCACHE
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select ARCH_DCACHE
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---help---
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Enable Xtensa D-Cache
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config XTENSA_ICACHE_LOCK
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bool "Use I-Cache lock & unlock feature"
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default n
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depends on XTENSA_HAVE_ICACHE
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depends on XTENSA_HAVE_ICACHE_LOCK
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select ARCH_ICACHE_LOCK
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---help---
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Enable Xtensa I-Cache lock & unlock feature
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config XTENSA_DCACHE_LOCK
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bool "Use D-Cache lock & unlock feature"
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default n
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depends on XTENSA_HAVE_DCACHE
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depends on XTENSA_HAVE_DCACHE_LOCK
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select ARCH_DCACHE_LOCK
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---help---
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Enable Xtensa D-Cache lock & unlock feature
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config XTENSA_ONESHOT
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bool "Xtensa oneshot lower half driver"
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default n
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depends on ONESHOT
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---help---
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Enable Xtensa oneshot driver.
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config ARCH_FAMILY_LX6
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bool
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default n
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---help---
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Cadence® Tensilica® Xtensa® LX6 data plane processing unit (DPU).
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The LX6 is a configurable and extensible processor core.
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config ARCH_FAMILY_LX7
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bool
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default n
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---help---
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Cadence® Tensilica® Xtensa® LX7 data plane processing unit (DPU).
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The LX7 is a configurable and extensible processor core.
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config ARCH_CHIP
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string
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default "esp32" if ARCH_CHIP_ESP32
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default "esp32s2" if ARCH_CHIP_ESP32S2
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default "esp32s3" if ARCH_CHIP_ESP32S3
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config XTENSA_CP_LAZY
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bool "Lazy co-processor state restoration"
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default n
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depends on EXPERIMENTAL
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---help---
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NuttX logic saves and restores the co-processor enabled (CPENABLE)
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register on each context switch. This has disadvantages in that (1)
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co-processor context will be saved and restored even if the co-
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processor was never used, and (2) tasks must explicitly enable and
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disable co-processors.
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An alternative, "lazy" co-processor state restore is enabled with
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this option. That logic works like as follows:
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a. CPENABLE is set to zero on each context switch, disabling all co-
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processors.
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b. If/when the task attempts to use the disabled co-processor, an
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exception occurs
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c. The co-processor exception handler re-enables the co-processor.
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config XTENSA_USE_OVLY
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bool
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default n
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---help---
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Enable code overlay support. This option is currently unsupported.
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config XTENSA_CP_INITSET
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hex "Default co-processor enables"
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default 0x0001
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range 0 0xffff
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depends on !XTENSA_CP_LAZY
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---help---
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Co-processors may be enabled on a thread by calling xtensa_coproc_enable()
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and disabled by calling xtensa_coproc_disable(). Some co-processors
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should be enabled on all threads by default. That set of co-processors
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is provided by CONFIG_XTENSA_CP_INITSET. Each bit corresponds to one
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coprocessor with the same bit layout as for the CPENABLE register.
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config XTENSA_DUMPBT_ON_ASSERT
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bool "Dump backtrace on assertions"
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default y
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depends on DEBUG_ALERT
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---help---
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Enable a backtrace dump on assertions.
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config XTENSA_BTDEPTH
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int "Backtrace depth"
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default 50
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depends on XTENSA_DUMPBT_ON_ASSERT
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---help---
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This is the depth of the backtrace.
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config XTENSA_INTBACKTRACE
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bool "Full backtrace from interrupts"
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default n
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depends on XTENSA_DUMPBT_ON_ASSERT
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---help---
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Add necessary logic to be able to have a full backtrace from an interrupt context.
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config XTENSA_IMEM_USE_SEPARATE_HEAP
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bool "Use a separate heap for internal memory"
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select ARCH_HAVE_EXTRA_HEAPS
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default n
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---help---
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This is a separate internal heap that's used by drivers when certain operations
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are not possible with the provided buffer(s).
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Mainly, when the provided buffer comes from external RAM and a DMA or flash
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operation is going to be performed.
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This separate heap will be part of the internal DRAM.
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config XTENSA_IMEM_REGION_SIZE
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hex "DRAM region size for internal use"
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depends on XTENSA_IMEM_USE_SEPARATE_HEAP
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default 0x18000
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config XTENSA_EXTMEM_BSS
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bool "Allow BSS section in external memory"
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default n
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---help---
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Adds a section and an attribute that allows to force variables into
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the external memory.
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config XTENSA_SEMIHOSTING_HOSTFS
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bool "Semihosting HostFS"
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depends on FS_HOSTFS
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---help---
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Mount HostFS through semihosting.
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This doesn't support some directory operations like readdir because
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of the limitations of semihosting mechanism.
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if XTENSA_SEMIHOSTING_HOSTFS
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config XTENSA_SEMIHOSTING_HOSTFS_CACHE_COHERENCE
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bool "Cache coherence in semihosting hostfs"
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depends on ARCH_DCACHE
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---help---
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Flush & Invalidte cache before & after sim call.
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endif
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choice
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prompt "Toolchain Selection"
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default XTENSA_TOOLCHAIN_ESP
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config XTENSA_TOOLCHAIN_XCC
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bool "Xtensa Toolchain use GCC as front end"
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select ARCH_TOOLCHAIN_GNU
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config XTENSA_TOOLCHAIN_XCLANG
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bool "Xtensa Toolchain use CLANG as front end"
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select ARCH_TOOLCHAIN_CLANG
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config XTENSA_TOOLCHAIN_ESP
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bool "ESP toolchain for xtensa"
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select ARCH_TOOLCHAIN_GNU
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endchoice
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source "arch/xtensa/src/lx6/Kconfig"
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if ARCH_CHIP_ESP32
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source "arch/xtensa/src/esp32/Kconfig"
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endif
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source "arch/xtensa/src/lx7/Kconfig"
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if ARCH_CHIP_ESP32S2
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source "arch/xtensa/src/esp32s2/Kconfig"
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endif
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if ARCH_CHIP_ESP32S3
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source "arch/xtensa/src/esp32s3/Kconfig"
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endif
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endif # ARCH_XTENSA
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