dytang d7cc3f9275 RISC-V: workaround for the RV64 SoC which does not has mem mapped MTIMER currten value regs.		2022-04-27 22:48:54 +08:00
..
include	RISC-V: Combine 3 variables that depend on CPU amount into one	2022-04-12 01:59:35 +08:00
src	RISC-V: workaround for the RV64 SoC which does not has mem mapped MTIMER currten value regs.	2022-04-27 22:48:54 +08:00
Kconfig	arch: risc-v: Do not enable FPU for K210 with QEMU	2022-04-22 14:52:04 +08:00