79 lines
3.7 KiB
C
79 lines
3.7 KiB
C
/****************************************************************************
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* arch/arm/src/armv7-a/mpcore.h
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* Generic Interrupt Controller Definitions
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Reference:
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* Cortex™-A9 MPCore, Revision: r4p1, Technical Reference Manual, ARM DDI
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* 0407I (ID091612).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_ARMV7_A_MPCORE_H
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#define __ARCH_ARM_SRC_ARMV7_A_MPCORE_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include "chip.h" /* For CHIP_MPCORE_VBASE */
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* MPCore registers are memory mapped and accessed through a processor
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* specific private address space via the SCU. The Cortex-A9 MCU chip.h
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* header file must provide the definition CHIP_MPCORE_VBASE to access this
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* the registers in this memory region.
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*/
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/* Peripheral Base Offsets **************************************************/
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#define MPCORE_SCU_OFFSET 0x0000 /* 0x0000-0x00fc SCU registers */
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#define MPCORE_ICC_OFFSET 0x0100 /* 0x0000-0x00FC Interrupt conroller interface */
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#define MPCORE_GTM_OFFSET 0x0200 /* 0x0200-0x02ff Global timer */
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/* 0x0300-0x05ff Reserved */
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#define MPCORE_PTM_OFFSET 0x0600 /* 0x0600-0x06ff Private timers and watchdogs */
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/* 0x0700-0x07ff Reserved */
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#define MPCORE_ICD_OFFSET 0x1000 /* 0x1000-0x1fff Interrupt Distributor */
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/* Peripheral Base Addresses ************************************************/
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#define MPCORE_SCU_VBASE (CHIP_MPCORE_VBASE+MPCORE_SCU_OFFSET)
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#define MPCORE_ICC_VBASE (CHIP_MPCORE_VBASE+MPCORE_ICC_OFFSET)
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#define MPCORE_GTM_VBASE (CHIP_MPCORE_VBASE+MPCORE_GTM_OFFSET)
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#define MPCORE_PTM_VBASE (CHIP_MPCORE_VBASE+MPCORE_PTM_OFFSET)
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#define MPCORE_ICD_VBASE (CHIP_MPCORE_VBASE+MPCORE_ICD_OFFSET)
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#endif /* __ARCH_ARM_SRC_ARMV7_A_MPCORE_H */
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