2997a49e51
STM32L4 RTC, PM: small fixes to subseconds handling, ADC power-management hooks
* STM32L4 ADC: add PM hooks from Motorola MDK
* STM32L4 RTC: add up_rtc_getdatetime_with_subseconds
* STM32 RTC: workaround for potential subseconds race condition
In all recent STM32 chips reading either RTC_SSR or RTC_TR is supposed to lock
the values in the higher-order calendar shadow registers until RTC_DR is read.
However many old chips have in their errata this silicon bug (at least F401xB/C,
F42xx, F43xx, L15xxE, L15xVD and likely others):
"When reading the calendar registers with BYPSHAD=0, the RTC_TR and RTC_DR
registers may not be locked after reading the RTC_SSR register. This happens
if the read operation is initiated one APB clock period before the shadow
registers are updated. This can result in a non-consistency of the three
registers. Similarly, RTC_DR register can be updated after reading the RTC_TR
register instead of being locked."
* STM32L4 RTC: correct RTC_SSR and RTC_TR read ordering
In all recent STM32 chips reading either RTC_SSR or RTC_TR is supposed to lock
the values in the higher-order calendar shadow registers until RTC_DR is read.
Change the register read ordering to match this and don't keep a workaround
for a hypothetical race condition (not in any L4 errata, lets for once assume
ST's silicon works as it is documented...)
* STM32L4 PM: remove useless #ifdefs and old non-L4 STM32 code
Approved-by: Gregory Nutt <gnutt@nuttx.org>
108 lines
3.6 KiB
C
108 lines
3.6 KiB
C
/****************************************************************************
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* arch/arm/src/stm32l4/stm32l4_pmlpr.c
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*
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* Copyright (C) 2012, 2017 Gregory Nutt. All rights reserved.
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* Copyright (C) 2015 Motorola Mobility, LLC. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdbool.h>
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#include "up_arch.h"
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#include "nvic.h"
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#include "stm32l4_pwr.h"
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#include "stm32l4_pm.h"
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#include "stm32l4_rcc.h"
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: stm32l4_pmlpr
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*
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* Description:
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* Enter Low-Power Run (LPR) mode.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* Zero means that LPR was successfully entered. Otherwise, LPR mode was not
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* entered and a negated errno value is returned to indicate the cause of the
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* failure.
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*
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****************************************************************************/
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int stm32l4_pmlpr(void)
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{
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uint32_t regval;
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/* Enable MSI clock */
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regval = getreg32(STM32L4_RCC_CR);
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regval |= RCC_CR_MSION;
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/* Set MSI clock to 2 MHz */
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regval &= ~RCC_CR_MSIRANGE_MASK;
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regval |= RCC_CR_MSIRANGE_2M; /* 2 MHz */
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regval |= RCC_CR_MSIRGSEL; /* Select new MSIRANGE */
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putreg32(regval, STM32L4_RCC_CR);
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/* Select MSI clock as system clock source */
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regval = getreg32(STM32L4_RCC_CFGR);
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regval &= ~RCC_CFGR_SW_MASK;
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regval |= RCC_CFGR_SW_MSI;
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putreg32(regval, STM32L4_RCC_CFGR);
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/* Wait until the MSI source is used as the system clock source */
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while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_MSI)
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{
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}
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/* Enable Low-Power Run */
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regval = getreg32(STM32L4_PWR_CR1);
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regval |= PWR_CR1_LPR;
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putreg32(regval, STM32L4_PWR_CR1);
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return OK;
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}
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