037c9ea0a4
Summary The naming standard at https://cwiki.apache.org/confluence/display/NUTTX/Naming+FAQ requires that all MCU-private files begin with the name of the architecture, not up_. This PR addresses only these name changes for the up_*.h files. There are only three, but almost 1680 files that include them: up_arch.h up_internal.h up_vfork.h The only change to the files is from including up_arch.h to arm_arch.h (for example). The entire job required to be compatible with that Naming Convention will also require changing the naming of the up_() functions that are used only within arch/arm and board/arm. Impact There should be not impact of this change (other that one step toward more consistent naming). Testing stm32f4discovery:netnsh
497 lines
18 KiB
C
497 lines
18 KiB
C
/****************************************************************************
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* arch/arm/src/am335x/am335x_gpio.c
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*
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* Copyright (C) 2018 Petro Karashchenko. All rights reserved.
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* Author: Petro Karashchenko <petro.karashchneko@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <errno.h>
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#include <nuttx/irq.h>
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#include "chip.h"
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#include "arm_arch.h"
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#include "am335x_pinmux.h"
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#include "am335x_gpio.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define AM335X_PADCTL_INVALID 255
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/****************************************************************************
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* Private Data
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****************************************************************************/
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const uintptr_t g_gpiobase[AM335X_GPIO_NPORTS] =
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{
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AM335X_GPIO0_VADDR, /* GPIO0 */
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AM335X_GPIO1_VADDR, /* GPIO1 */
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AM335X_GPIO2_VADDR, /* GPIO2 */
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AM335X_GPIO3_VADDR /* GPIO3 */
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};
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static const uint8_t g_gpio0_padctl[AM335X_GPIO_NPINS] =
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{
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AM335X_PADCTL_MDIO_INDEX, /* GPIO0 Pin 0 */
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AM335X_PADCTL_MDC_INDEX, /* GPIO0 Pin 1 */
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AM335X_PADCTL_SPI0_SCLK_INDEX, /* GPIO0 Pin 2 */
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AM335X_PADCTL_SPI0_D0_INDEX, /* GPIO0 Pin 3 */
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AM335X_PADCTL_SPI0_D1_INDEX, /* GPIO0 Pin 4 */
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AM335X_PADCTL_SPI0_CS0_INDEX, /* GPIO0 Pin 5 */
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AM335X_PADCTL_SPI0_CS1_INDEX, /* GPIO0 Pin 6 */
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AM335X_PADCTL_ECAP0_IN_PWM0_OUT_INDEX, /* GPIO0 Pin 7 */
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AM335X_PADCTL_LCD_DATA12_INDEX, /* GPIO0 Pin 8 */
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AM335X_PADCTL_LCD_DATA13_INDEX, /* GPIO0 Pin 9 */
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AM335X_PADCTL_LCD_DATA14_INDEX, /* GPIO0 Pin 10 */
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AM335X_PADCTL_LCD_DATA15_INDEX, /* GPIO0 Pin 11 */
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AM335X_PADCTL_UART1_CTSN_INDEX, /* GPIO0 Pin 12 */
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AM335X_PADCTL_UART1_RTSN_INDEX, /* GPIO0 Pin 13 */
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AM335X_PADCTL_UART1_RXD_INDEX, /* GPIO0 Pin 14 */
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AM335X_PADCTL_UART1_TXD_INDEX, /* GPIO0 Pin 15 */
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AM335X_PADCTL_MII1_TXD3_INDEX, /* GPIO0 Pin 16 */
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AM335X_PADCTL_MII1_TXD2_INDEX, /* GPIO0 Pin 17 */
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AM335X_PADCTL_USB0_DRVVBUS_INDEX, /* GPIO0 Pin 18 */
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AM335X_PADCTL_XDMA_EVENT_INTR0_INDEX, /* GPIO0 Pin 19 */
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AM335X_PADCTL_XDMA_EVENT_INTR1_INDEX, /* GPIO0 Pin 20 */
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AM335X_PADCTL_MII1_TXD1_INDEX, /* GPIO0 Pin 21 */
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AM335X_PADCTL_GPMC_AD8_INDEX, /* GPIO0 Pin 22 */
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AM335X_PADCTL_GPMC_AD9_INDEX, /* GPIO0 Pin 23 */
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AM335X_PADCTL_INVALID, /* GPIO0 Pin 24 */
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AM335X_PADCTL_INVALID, /* GPIO0 Pin 25 */
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AM335X_PADCTL_GPMC_AD10_INDEX, /* GPIO0 Pin 26 */
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AM335X_PADCTL_GPMC_AD11_INDEX, /* GPIO0 Pin 27 */
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AM335X_PADCTL_MII1_TXD0_INDEX, /* GPIO0 Pin 28 */
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AM335X_PADCTL_RMII1_REF_CLK_INDEX, /* GPIO0 Pin 29 */
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AM335X_PADCTL_GPMC_WAIT0_INDEX, /* GPIO0 Pin 30 */
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AM335X_PADCTL_GPMC_WPN_INDEX /* GPIO0 Pin 31 */
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};
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static const uint8_t g_gpio1_padctl[AM335X_GPIO_NPINS] =
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{
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AM335X_PADCTL_GPMC_AD0_INDEX, /* GPIO1 Pin 0 */
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AM335X_PADCTL_GPMC_AD1_INDEX, /* GPIO1 Pin 1 */
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AM335X_PADCTL_GPMC_AD2_INDEX, /* GPIO1 Pin 2 */
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AM335X_PADCTL_GPMC_AD3_INDEX, /* GPIO1 Pin 3 */
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AM335X_PADCTL_GPMC_AD4_INDEX, /* GPIO1 Pin 4 */
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AM335X_PADCTL_GPMC_AD5_INDEX, /* GPIO1 Pin 5 */
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AM335X_PADCTL_GPMC_AD6_INDEX, /* GPIO1 Pin 6 */
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AM335X_PADCTL_GPMC_AD7_INDEX, /* GPIO1 Pin 7 */
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AM335X_PADCTL_UART0_CTSN_INDEX, /* GPIO1 Pin 8 */
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AM335X_PADCTL_UART0_RTSN_INDEX, /* GPIO1 Pin 9 */
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AM335X_PADCTL_UART0_RXD_INDEX, /* GPIO1 Pin 10 */
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AM335X_PADCTL_UART0_TXD_INDEX, /* GPIO1 Pin 11 */
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AM335X_PADCTL_GPMC_AD12_INDEX, /* GPIO1 Pin 12 */
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AM335X_PADCTL_GPMC_AD13_INDEX, /* GPIO1 Pin 13 */
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AM335X_PADCTL_GPMC_AD14_INDEX, /* GPIO1 Pin 14 */
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AM335X_PADCTL_GPMC_AD15_INDEX, /* GPIO1 Pin 15 */
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AM335X_PADCTL_GPMC_A0_INDEX, /* GPIO1 Pin 16 */
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AM335X_PADCTL_GPMC_A1_INDEX, /* GPIO1 Pin 17 */
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AM335X_PADCTL_GPMC_A2_INDEX, /* GPIO1 Pin 18 */
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AM335X_PADCTL_GPMC_A3_INDEX, /* GPIO1 Pin 19 */
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AM335X_PADCTL_GPMC_A4_INDEX, /* GPIO1 Pin 20 */
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AM335X_PADCTL_GPMC_A5_INDEX, /* GPIO1 Pin 21 */
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AM335X_PADCTL_GPMC_A6_INDEX, /* GPIO1 Pin 22 */
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AM335X_PADCTL_GPMC_A7_INDEX, /* GPIO1 Pin 23 */
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AM335X_PADCTL_GPMC_A8_INDEX, /* GPIO1 Pin 24 */
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AM335X_PADCTL_GPMC_A9_INDEX, /* GPIO1 Pin 25 */
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AM335X_PADCTL_GPMC_A10_INDEX, /* GPIO1 Pin 26 */
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AM335X_PADCTL_GPMC_A11_INDEX, /* GPIO1 Pin 27 */
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AM335X_PADCTL_GPMC_BEN1_INDEX, /* GPIO1 Pin 28 */
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AM335X_PADCTL_GPMC_CSN0_INDEX, /* GPIO1 Pin 29 */
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AM335X_PADCTL_GPMC_CSN1_INDEX, /* GPIO1 Pin 30 */
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AM335X_PADCTL_GPMC_CSN2_INDEX, /* GPIO1 Pin 31 */
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};
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static const uint8_t g_gpio2_padctl[AM335X_GPIO_NPINS] =
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{
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AM335X_PADCTL_GPMC_CSN3_INDEX, /* GPIO2 Pin 0 */
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AM335X_PADCTL_GPMC_CLK_INDEX, /* GPIO2 Pin 1 */
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AM335X_PADCTL_GPMC_ADVN_ALE_INDEX, /* GPIO2 Pin 2 */
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AM335X_PADCTL_GPMC_OEN_REN_INDEX, /* GPIO2 Pin 3 */
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AM335X_PADCTL_GPMC_WEN_INDEX, /* GPIO2 Pin 4 */
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AM335X_PADCTL_GPMC_BEN0_CLE_INDEX, /* GPIO2 Pin 5 */
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AM335X_PADCTL_LCD_DATA0_INDEX, /* GPIO2 Pin 6 */
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AM335X_PADCTL_LCD_DATA1_INDEX, /* GPIO2 Pin 7 */
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AM335X_PADCTL_LCD_DATA2_INDEX, /* GPIO2 Pin 8 */
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AM335X_PADCTL_LCD_DATA3_INDEX, /* GPIO2 Pin 9 */
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AM335X_PADCTL_LCD_DATA4_INDEX, /* GPIO2 Pin 10 */
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AM335X_PADCTL_LCD_DATA5_INDEX, /* GPIO2 Pin 11 */
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AM335X_PADCTL_LCD_DATA6_INDEX, /* GPIO2 Pin 12 */
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AM335X_PADCTL_LCD_DATA7_INDEX, /* GPIO2 Pin 13 */
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AM335X_PADCTL_LCD_DATA8_INDEX, /* GPIO2 Pin 14 */
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AM335X_PADCTL_LCD_DATA9_INDEX, /* GPIO2 Pin 15 */
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AM335X_PADCTL_LCD_DATA10_INDEX, /* GPIO2 Pin 16 */
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AM335X_PADCTL_LCD_DATA11_INDEX, /* GPIO2 Pin 17 */
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AM335X_PADCTL_MII1_RXD3_INDEX, /* GPIO2 Pin 18 */
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AM335X_PADCTL_MII1_RXD2_INDEX, /* GPIO2 Pin 19 */
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AM335X_PADCTL_MII1_RXD1_INDEX, /* GPIO2 Pin 20 */
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AM335X_PADCTL_MII1_RXD0_INDEX, /* GPIO2 Pin 21 */
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AM335X_PADCTL_LCD_VSYNC_INDEX, /* GPIO2 Pin 22 */
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AM335X_PADCTL_LCD_HSYNC_INDEX, /* GPIO2 Pin 23 */
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AM335X_PADCTL_LCD_PCLK_INDEX, /* GPIO2 Pin 24 */
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AM335X_PADCTL_LCD_AC_BIAS_EN_INDEX, /* GPIO2 Pin 25 */
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AM335X_PADCTL_MMC0_DAT3_INDEX, /* GPIO2 Pin 26 */
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AM335X_PADCTL_MMC0_DAT2_INDEX, /* GPIO2 Pin 27 */
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AM335X_PADCTL_MMC0_DAT1_INDEX, /* GPIO2 Pin 28 */
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AM335X_PADCTL_MMC0_DAT0_INDEX, /* GPIO2 Pin 29 */
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AM335X_PADCTL_MMC0_CLK_INDEX, /* GPIO2 Pin 30 */
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AM335X_PADCTL_MMC0_CMD_INDEX, /* GPIO2 Pin 31 */
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};
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static const uint8_t g_gpio3_padctl[AM335X_GPIO_NPINS] =
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{
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AM335X_PADCTL_MII1_COL_INDEX, /* GPIO3 Pin 0 */
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AM335X_PADCTL_MII1_CRS_INDEX, /* GPIO3 Pin 1 */
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AM335X_PADCTL_MII1_RX_ER_INDEX, /* GPIO3 Pin 2 */
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AM335X_PADCTL_MII1_TX_EN_INDEX, /* GPIO3 Pin 3 */
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AM335X_PADCTL_MII1_RX_DV_INDEX, /* GPIO3 Pin 4 */
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AM335X_PADCTL_I2C0_SDA_INDEX, /* GPIO3 Pin 5 */
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AM335X_PADCTL_I2C0_SCL_INDEX, /* GPIO3 Pin 6 */
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AM335X_PADCTL_EMU0_INDEX, /* GPIO3 Pin 7 */
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AM335X_PADCTL_EMU1_INDEX, /* GPIO3 Pin 8 */
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AM335X_PADCTL_MII1_TX_CLK_INDEX, /* GPIO3 Pin 9 */
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AM335X_PADCTL_MII1_RX_CLK_INDEX, /* GPIO3 Pin 10 */
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AM335X_PADCTL_INVALID, /* GPIO3 Pin 11 */
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AM335X_PADCTL_INVALID, /* GPIO3 Pin 12 */
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AM335X_PADCTL_USB1_DRVVBUS_INDEX, /* GPIO3 Pin 13 */
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AM335X_PADCTL_MCASP0_ACLKX_INDEX, /* GPIO3 Pin 14 */
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AM335X_PADCTL_MCASP0_FSX_INDEX, /* GPIO3 Pin 15 */
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AM335X_PADCTL_MCASP0_AXR0_INDEX, /* GPIO3 Pin 16 */
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AM335X_PADCTL_MCASP0_AHCLKR_INDEX, /* GPIO3 Pin 17 */
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AM335X_PADCTL_MCASP0_ACLKR_INDEX, /* GPIO3 Pin 18 */
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AM335X_PADCTL_MCASP0_FSR_INDEX, /* GPIO3 Pin 19 */
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AM335X_PADCTL_MCASP0_AXR1_INDEX, /* GPIO3 Pin 20 */
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AM335X_PADCTL_MCASP0_AHCLKX_INDEX, /* GPIO3 Pin 21 */
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AM335X_PADCTL_INVALID, /* GPIO3 Pin 22 */
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AM335X_PADCTL_INVALID, /* GPIO3 Pin 23 */
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AM335X_PADCTL_INVALID, /* GPIO3 Pin 24 */
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AM335X_PADCTL_INVALID, /* GPIO3 Pin 25 */
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AM335X_PADCTL_INVALID, /* GPIO3 Pin 26 */
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AM335X_PADCTL_INVALID, /* GPIO3 Pin 27 */
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AM335X_PADCTL_INVALID, /* GPIO3 Pin 28 */
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AM335X_PADCTL_INVALID, /* GPIO3 Pin 29 */
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AM335X_PADCTL_INVALID, /* GPIO3 Pin 30 */
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AM335X_PADCTL_INVALID, /* GPIO3 Pin 31 */
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};
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static const uint8_t *g_gpio_padctl[AM335X_GPIO_NPORTS] =
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{
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g_gpio0_padctl, /* GPIO0 */
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g_gpio1_padctl, /* GPIO1 */
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g_gpio2_padctl, /* GPIO2 */
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g_gpio3_padctl, /* GPIO3 */
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};
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: am335x_gpio_dirout
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****************************************************************************/
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static inline void am335x_gpio_dirout(int port, int pin)
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{
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uint32_t regval = getreg32(AM335X_GPIO_OER(am335x_gpion_vbase(port)));
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regval &= ~GPIO_PIN(pin);
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putreg32(regval, AM335X_GPIO_OER(am335x_gpion_vbase(port)));
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}
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/****************************************************************************
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* Name: am335x_gpio_dirin
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****************************************************************************/
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static inline void am335x_gpio_dirin(int port, int pin)
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{
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uint32_t regval = getreg32(AM335X_GPIO_OER(am335x_gpion_vbase(port)));
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regval |= GPIO_PIN(pin);
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putreg32(regval, AM335X_GPIO_OER(am335x_gpion_vbase(port)));
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}
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/****************************************************************************
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* Name: am335x_gpio_setoutput
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****************************************************************************/
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static void am335x_gpio_setoutput(int port, int pin, bool value)
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{
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uint32_t regval = GPIO_PIN(pin);
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putreg32(regval, value ? AM335X_GPIO_SDOR(am335x_gpion_vbase(port)) :
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AM335X_GPIO_CDOR(am335x_gpion_vbase(port)));
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}
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/****************************************************************************
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* Name: am335x_gpio_getinput
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****************************************************************************/
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static inline bool am335x_gpio_getinput(int port, int pin)
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{
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uint32_t regval = getreg32(AM335X_GPIO_DIR(am335x_gpion_vbase(port)));
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return ((regval & GPIO_PIN(pin)) != 0);
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}
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/****************************************************************************
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* Name: am335x_gpio_configinput
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****************************************************************************/
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static int am335x_gpio_configinput(gpio_pinset_t pinset)
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{
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int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
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int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
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pinmux_pinset_t muxset;
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uintptr_t regaddr;
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uint8_t index;
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/* Configure pin as in input */
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am335x_gpio_dirin(port, pin);
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/* Configure pin interrupt levels */
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am335x_gpioirq(pinset);
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/* Configure pin as a GPIO */
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index = g_gpio_padctl[port][pin];
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if (index >= AM335X_PADCTL_NREGISTERS)
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{
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return -EINVAL;
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}
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/* Ensure that RX is enabled */
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pinset |= PINMUX_MODE7 | PINMUX_RX_ENABLE;
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/* Configure pin pad settings */
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regaddr = AM335X_PADCTL_ADDRESS(index);
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muxset = (pinmux_pinset_t)((pinset & GPIO_PINMUX_MASK) >> GPIO_PINMUX_SHIFT);
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return am335x_pinmux_configure(regaddr, muxset);
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}
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/****************************************************************************
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* Name: am335x_gpio_configoutput
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****************************************************************************/
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static inline int am335x_gpio_configoutput(gpio_pinset_t pinset)
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{
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int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
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int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
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bool value = ((pinset & GPIO_OUTPUT_ONE) != 0);
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/* Set the output value */
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am335x_gpio_setoutput(port, pin, value);
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/* Convert the configured input GPIO to an output */
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am335x_gpio_dirout(port, pin);
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return OK;
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}
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/****************************************************************************
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* Name: am335x_gpio_configperiph
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****************************************************************************/
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static inline int am335x_gpio_configperiph(gpio_pinset_t pinset)
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{
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pinmux_pinset_t muxset;
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uintptr_t regaddr;
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unsigned int index;
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/* Configure pin as a peripheral */
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index = ((pinset & GPIO_PADCTL_MASK) >> GPIO_PADCTL_SHIFT);
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regaddr = AM335X_PADCTL_ADDRESS(index);
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muxset = (pinmux_pinset_t)((pinset & GPIO_PINMUX_MASK) >> GPIO_PINMUX_SHIFT);
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return am335x_pinmux_configure(regaddr, muxset);
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: am335x_gpio_config
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*
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* Description:
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* Configure a GPIO pin based on pin-encoded description of the pin.
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*
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****************************************************************************/
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int am335x_gpio_config(gpio_pinset_t pinset)
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{
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irqstate_t flags;
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int ret;
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/* Configure the pin as an input initially to avoid any spurious outputs */
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flags = enter_critical_section();
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/* Configure based upon the pin mode */
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switch (pinset & GPIO_MODE_MASK)
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{
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case GPIO_INPUT:
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{
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/* Configure the pin as a GPIO input */
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ret = am335x_gpio_configinput(pinset);
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}
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break;
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case GPIO_OUTPUT:
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{
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/* First configure the pin as a GPIO input to avoid output
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* glitches.
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*/
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ret = am335x_gpio_configinput(pinset);
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if (ret >= 0)
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{
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/* Convert the input to an output */
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ret = am335x_gpio_configoutput(pinset);
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}
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}
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break;
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case GPIO_PERIPH:
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{
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/* Configure the pin as a peripheral */
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ret = am335x_gpio_configperiph(pinset);
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}
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break;
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default:
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ret = -EINVAL;
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break;
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}
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leave_critical_section(flags);
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return ret;
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}
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/************************************************************************************
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* Name: am335x_gpio_write
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*
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* Description:
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* Write one or zero to the selected GPIO pin
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|
*
|
|
************************************************************************************/
|
|
|
|
void am335x_gpio_write(gpio_pinset_t pinset, bool value)
|
|
{
|
|
irqstate_t flags;
|
|
int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
|
int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
|
|
|
flags = enter_critical_section();
|
|
am335x_gpio_setoutput(port, pin, value);
|
|
leave_critical_section(flags);
|
|
}
|
|
|
|
/************************************************************************************
|
|
* Name: am335x_gpio_read
|
|
*
|
|
* Description:
|
|
* Read one or zero from the selected GPIO pin
|
|
*
|
|
************************************************************************************/
|
|
|
|
bool am335x_gpio_read(gpio_pinset_t pinset)
|
|
{
|
|
irqstate_t flags;
|
|
int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
|
int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
|
bool value;
|
|
|
|
flags = enter_critical_section();
|
|
value = am335x_gpio_getinput(port, pin);
|
|
leave_critical_section(flags);
|
|
return value;
|
|
}
|
|
|
|
/************************************************************************************
|
|
* Name: am335x_periph_gpio
|
|
*
|
|
* Description:
|
|
* Return GPIO pinset that correspond to provided peripheral pinset.
|
|
*
|
|
************************************************************************************/
|
|
|
|
gpio_pinset_t am335x_periph_gpio(gpio_pinset_t pinset)
|
|
{
|
|
unsigned int index;
|
|
int port;
|
|
int pin;
|
|
|
|
if ((pinset & GPIO_MODE_MASK) == GPIO_PERIPH)
|
|
{
|
|
index = ((pinset & GPIO_PADCTL_MASK) >> GPIO_PADCTL_SHIFT);
|
|
for (port = 0; port < AM335X_GPIO_NPORTS; port++)
|
|
{
|
|
for (pin = 0; pin < AM335X_GPIO_NPINS; pin++)
|
|
{
|
|
if (index == g_gpio_padctl[port][pin])
|
|
{
|
|
return (GPIO_INPUT | (port << GPIO_PORT_SHIFT) |
|
|
(pin << GPIO_PIN_SHIFT));
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return GPIO_MODE_MASK;
|
|
}
|