chao an da4c229312 arch/riscv: replace atomic operations to AMO ... RISC-V provided fetch-and-op style atomic primitives as they scale to highly parallel systems better than LR/SC or CAS. A simple microarchitecture can implement AMOs using the LR/SC primitives, provided the implementation can guarantee the AMO eventually completes. More complex implementations might also implement AMOs at memory controllers, and can optimize away fetching the original value when the destination is x0. Signed-off-by: chao an <anchao@lixiang.com> Co-authored-by: Petro Karashchenko <petro.karashchenko@gmail.com>		2024-04-25 18:23:58 +09:00
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include	arch/risc-v: add support of save/restore vector registers	2024-04-23 16:18:46 -03:00
src	arch/riscv: replace atomic operations to AMO	2024-04-25 18:23:58 +09:00
CMakeLists.txt	cmake:init RISC-V cmake qemu-rv build	2023-10-26 21:01:46 +08:00
Kconfig	arch/risc-v: add support of save/restore vector registers	2024-04-23 16:18:46 -03:00