ESP32C3 use customized irq encoding so it's hard to share further code with other risc-v based chips, in this patch, we keep the exception number definition with risc-v spec. Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
ESP32C3 use customized irq encoding so it's hard to share further code with other risc-v based chips, in this patch, we keep the exception number definition with risc-v spec. Signed-off-by: Huang Qi <huangqi3@xiaomi.com>