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nuttx/arch/risc-v/include
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Yanfeng Liu a4b22fe999 risc-v/k230: initial Asymmetric Multi-Processing support 
K230 chip has two T-Head C908 RiscV cores, previously we run NuttX
on either little or big cores. This patch runs NuttX on both cores
with OpenAMP support via the RPTUN driver.

New additions:

- in arch/risc-v/src/k230
  - k230_rptun.c              K230 RPTUN driver
  - k230_rptun.h              K230 RPTUN driver header file

- in baords/risc-v/k230/canmv230
  - configs/master            Build config for master node
  - configs/remote            Build config for remote node
  - scripts/ld-rptun.script   Build script for RPTUN

Major changes:

- arch/risc-v/Kconfig         Select NUTTSBI_LATE_INIT upon NUTTSBI
- in arch/risc-v/include
  - k230/irq.h                Add UART3 IRQ defs
- in arch/risc-v/src/k230
  - Kconfig                   Add RPTUN related config items
  - Make.defs                 Add k230-rptun.c to sources
  - hardware/k230_memorymap.h Add K230 device and CSR defs
  - k230_hart.c               Add hart ctrl for RPTUN
  - k230_hart.h               Add hart ctrl for RPTUN
  - k230_mm_init.c            Add Svpmbt to support RPTUN
  - k230_start.c              Revised to support RPMsg UART
- in boards/risc-v/k230/canmv230
  - scripts/Make.defs         Add RPTUN script selection
  - src/canmv_init.c          Add RPTUN and RPMsg_UART initialization
- in Documentation/platforms/risc-v/k230/boards/canmv230
  - index.rst                 Add AMP usage information.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
2024-02-13 10:34:21 -03:00
..
bl602
bl808 arch/riscv: Add support for Bouffalo Lab BL808 SoC (T-Head C906) 2023-12-12 08:50:03 -08:00
c906
esp32c3 risc-v/espressif: Rename espressif/esp32c3 as esp32c3 2024-01-30 08:32:05 +01:00
esp32c3-legacy risc-v/esp32c3: Rename legacy approach esp32c3 as esp32c3-legacy 2024-01-30 08:32:05 +01:00
esp32c6 risc-v/espressif: Rename espressif/esp32c3 as esp32c3 2024-01-30 08:32:05 +01:00
esp32h2 risc-v/espressif: Rename espressif/esp32c3 as esp32c3 2024-01-30 08:32:05 +01:00
fe310
hpm6750 add hpmicro chip: hpm6750 2023-02-09 14:17:49 +08:00
jh7110 arch/risc-v: Add support for StarFive JH7110 SoC 2023-08-03 22:55:55 -07:00
k210
k230 risc-v/k230: initial Asymmetric Multi-Processing support 2024-02-13 10:34:21 -03:00
litex risc-v/litex: fix typo in litex/irq.h 2024-01-06 04:15:52 -08:00
mpfs risc-v/mpfs: add athena irq defines 2023-02-15 00:21:03 +08:00
qemu-rv
rv32m1
.gitignore
arch.h risc-v/addrenv: Improve the commenting on struct arch_addrenv_s 2023-11-02 21:52:23 +08:00
barriers.h riscv/barrier: Define more granular memory barriers 2023-06-14 16:14:57 -03:00
csr.h arch/risc-v: add status fields for VS and XS 2024-01-28 06:38:25 -08:00
elf.h riscv/arch_elf.c: Handle PCREL_HI20/LO12_I/S relocations correctly 2023-12-12 17:32:36 -08:00
inttypes.h
irq.h arch/risc-v: fix a few typos in comments 2023-12-31 07:25:51 -08:00
limits.h
mode.h Update mode.h to add CSR_TVEC 2023-12-23 20:43:47 -08:00
setjmp.h
spinlock.h
stdarg.h
syscall.h arch/risc-v: change up_saveusercontext to assembly code 2023-04-27 17:34:30 +08:00
types.h