b4ee19f5bd
Squashed commit of the following:
arch/arm/src/s32k1xx: Update peripheral input clocking for the way that things are done for the S32K1XX. Fix other misc. compilation/configuration issues.
arch/arm/src/s32k1xx: Clean up LPSPI and LPI2C naming for S32K1XX. Using S32K1XX clock functions to get peripheral input clock.
arch/arm/src/s32k1xx: Clone i.MXRT LPSPI and LPI2C support. i.MXRT uses the same IP as S32K1XX.
117 lines
6.0 KiB
C
117 lines
6.0 KiB
C
/************************************************************************************
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* arch/arm/include/s32k1xx/s32k11x_irq.h
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*
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* Copyright (C) 2019 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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/* This file should never be included directed but, rather, only indirectly through
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* nuttx/irq.h
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*/
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#ifndef __ARCH_ARM_INCLUDE_S32K1XX_S32K11XX_IRQ_H
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#define __ARCH_ARM_INCLUDE_S32K1XX_S32K11XX_IRQ_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
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* bits in the NVIC. This does, however, waste several words of memory in the IRQ
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* to handle mapping tables.
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*/
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/* Processor Exceptions (vectors 0-15) */
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#define S32K1XX_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
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/* Vector 0: Reset stack pointer value */
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/* Vector 1: Reset (not handler as an IRQ) */
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#define S32K1XX_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
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#define S32K1XX_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
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/* Vector 4-10: Reserved */
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#define S32K1XX_IRQ_SVCALL (11) /* Vector 11: SVC call */
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/* Vector 12-13: Reserved */
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#define S32K1XX_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
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#define S32K1XX_IRQ_SYSTICK (15) /* Vector 15: System tick */
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/* External interrupts (vectors >= 16). These definitions are chip-specific */
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#define S32K1XX_IRQ_INTERRUPT (16)
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#define S32K1XX_IRQ_DMACH0 (16) /* DMA channel 0 transfer complete */
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#define S32K1XX_IRQ_DMACH1 (17) /* DMA channel 1 transfer complete */
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#define S32K1XX_IRQ_DMACH2 (18) /* DMA channel 2 transfer complete */
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#define S32K1XX_IRQ_DMACH3 (19) /* DMA channel 3 transfer complete */
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#define S32K1XX_IRQ_DMACH_ERR (20) /* DMA error interrupt channels 0-15 */
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#define S32K1XX_IRQ_ERM (21) /* ERM single/double bit error */
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#define S32K1XX_IRQ_RTC_ALARM (22) /* RTC alarm interrupt */
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#define S32K1XX_IRQ_RTC_SEC (23) /* RTC seconds interrupt */
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#define S32K1XX_IRQ_LPTIMER (24) /* LPTIMER interrupt request */
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#define S32K1XX_IRQ_PORT (25) /* PORTA-E Interrupt */
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#define S32K1XX_IRQ_CAN0 (26) /* CAN0 OR'ed Interrupt */
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#define S32K1XX_IRQ_CAN0_0_31 (27) /* CAN0 OR'ed Message buffer (0-31) */
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#define S32K1XX_IRQ_FTM0_CH0_7 (28) /* FTM0 Channel 0..7 Interrupt */
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#define S32K1XX_IRQ_FTM0_FAULT (29) /* FTM0 Fault Interrupt */
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#define S32K1XX_IRQ_FTM0_OVERFLOW (30) /* FTM0 Counter Overflow/Reload Interrupt */
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#define S32K1XX_IRQ_FTM1_CH0_7 (31) /* FTM1 Channel 0..7 Interrupt */
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#define S32K1XX_IRQ_FTM1_FAULT (32) /* FTM1 Fault Interrupt */
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#define S32K1XX_IRQ_FTM1_OVERFLOW (33) /* FTM1 Counter Overflow/Reload Interrupt */
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#define S32K1XX_IRQ_FTFC (34) /* FTFC Command Complete, Collision, Double bit */
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#define S32K1XX_IRQ_PDB (35) /* PDB Interrupt */
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#define S32K1XX_IRQ_LPIT (36) /* LPIT Interrupt */
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#define S32K1XX_IRQ_PMC (37) /* PMC Interrupt */
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#define S32K1XX_IRQ_WDOG (38) /* WDOG interrupt request out before wdg reset out */
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#define S32K1XX_IRQ_RCM (39) /* RCM Asynchronous Interrupt */
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#define S32K1XX_IRQ_LPI2C0M (40) /* LPI2C Master/Slave Interrupt */
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#define S32K1XX_IRQ_LPI2C0S (40) /* LPI2C Master/Slave Interrupt */
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#define S32K1XX_IRQ_FLEXIO (41) /* FlexIO Interrupt */
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#define S32K1XX_IRQ_LPSPI0 (42) /* LPSPI0 Interrupt */
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#define S32K1XX_IRQ_LPSPI1 (43) /* LPSPI1 Interrupt */
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#define S32K1XX_IRQ_ADC0 (44) /* ADC0 Interrupt */
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#define S32K1XX_IRQ_CMP0 (45) /* CMP0 Interrupt */
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#define S32K1XX_IRQ_LPUART1 (46) /* LPUART1 Interrupt */
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#define S32K1XX_IRQ_LPUART0 (47) /* LPUART0 Interrupt */
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#define S32K1XX_IRQ_NIRQS (48)
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#define S32K1XX_IRQ_NEXTINT (S32K1XX_IRQ_NIRQS - S32K1XX_IRQ_INTERRUPT)
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/* Total number of IRQ numbers */
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#define NR_IRQS S32K1XX_IRQ_NIRQS
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#endif /* __ARCH_ARM_INCLUDE_S32K1XX_S32K11XX_IRQ_H */
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