d42fc094fa
arm: stm32: codestyle fixes
* arm: stm32f0l0g0: codestyle fixes
After the board restructuration is time for codestyle cleanup
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arm: stm32f7: codestyle fixes
After the board restructuration is time for codestyle cleanup
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arm: stm32h7: codestyle fixes
After the board restructuration is time for codestyle cleanup
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arm: stm32l4: codestyle fixes
After the board restructuration is time for codestyle cleanup
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arm: stm32: codestyle fixes
After the board restructuration is time for codestyle cleanup
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
276 lines
10 KiB
C
276 lines
10 KiB
C
/****************************************************************************
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* boards/arm/stm32/stm32f3discovery/include/board.h
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*
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* Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_STM32_STM32F3DISCOVERY_INCLUDE_BOARD_H
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#define __BOARDS_ARM_STM32_STM32F3DISCOVERY_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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#include "stm32_rcc.h"
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#include "stm32.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *************************************************************************/
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/* HSI - Internal 8 MHz RC Oscillator
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* LSI - 32 KHz RC
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* HSE - On-board crystal frequency is 8MHz
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* LSE - 32.768 kHz
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*/
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#define STM32_BOARD_XTAL 8000000ul /* X1 on board */
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#define STM32_HSI_FREQUENCY 8000000ul
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#define STM32_LSI_FREQUENCY 40000 /* Between 30kHz and 60kHz */
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_LSE_FREQUENCY 32768 /* X2 on board */
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/* PLL source is HSE/1, PLL multipler is 9: PLL frequency is 8MHz (XTAL) x 9 = 72MHz */
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#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC
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#define STM32_CFGR_PLLXTPRE 0
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#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9
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#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL)
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/* Use the PLL and set the SYSCLK source to be the PLL */
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#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL
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#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
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#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY
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/* AHB clock (HCLK) is SYSCLK (72MHz) */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
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#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
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/* APB2 clock (PCLK2) is HCLK (72MHz) */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
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#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
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#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY) /* Timers 1 and 8, 15-17 */
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/* APB2 timers 1 and 8, 15-17 will receive PCLK2. */
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/* Timers driven from APB2 will be PCLK2 */
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#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB1_TIM15_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB1_TIM16_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB1_TIM17_CLKIN (STM32_PCLK2_FREQUENCY)
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/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* APB1 timers 2-7 will be twice PCLK1 */
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
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/* USB divider -- Divide PLL clock by 1.5 */
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#define STM32_CFGR_USBPRE 0
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
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* otherwise frequency is 2xAPBx.
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* Note: TIM1,8 are on APB2, others on APB1
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*/
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#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
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#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
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#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
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#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
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#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
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#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
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#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
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#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY
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/* LED definitions ******************************************************************/
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/* The STM32F3Discovery board has ten LEDs. Two of these are controlled by logic on
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* the board and are not available for software control:
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*
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* LD1 PWR: red LED indicates that the board is powered.
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* LD2 COM: LD2 default status is red. LD2 turns to green to indicate that
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* communications are in progress between the PC and the ST-LINK/V2.
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*
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* And eight can be controlled by software:
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*
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* User LD3: red LED is a user LED connected to the I/O PE9 of the STM32F303VCT6.
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* User LD4: blue LED is a user LED connected to the I/O PE8 of the STM32F303VCT6.
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* User LD5: orange LED is a user LED connected to the I/O PE10 of the STM32F303VCT6.
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* User LD6: green LED is a user LED connected to the I/O PE15 of the STM32F303VCT6.
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* User LD7: green LED is a user LED connected to the I/O PE11 of the STM32F303VCT6.
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* User LD8: orange LED is a user LED connected to the I/O PE14 of the STM32F303VCT6.
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* User LD9: blue LED is a user LED connected to the I/O PE12 of the STM32F303VCT6.
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* User LD10: red LED is a user LED connected to the I/O PE13 of the STM32F303VCT6.
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*
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* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any
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* way. The following definitions are used to access individual LEDs.
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_LED1 0 /* User LD3 */
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#define BOARD_LED2 1 /* User LD4 */
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#define BOARD_LED3 2 /* User LD5 */
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#define BOARD_LED4 3 /* User LD6 */
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#define BOARD_LED5 4 /* User LD7 */
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#define BOARD_LED6 5 /* User LD8 */
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#define BOARD_LED7 6 /* User LD9 */
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#define BOARD_LED8 7 /* User LD10 */
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#define BOARD_NLEDS 8
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/* LED bits for use with board_userled_all() */
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#define BOARD_LED1_BIT (1 << BOARD_LED1)
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#define BOARD_LED2_BIT (1 << BOARD_LED2)
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#define BOARD_LED3_BIT (1 << BOARD_LED3)
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#define BOARD_LED4_BIT (1 << BOARD_LED4)
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#define BOARD_LED5_BIT (1 << BOARD_LED5)
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#define BOARD_LED6_BIT (1 << BOARD_LED6)
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#define BOARD_LED7_BIT (1 << BOARD_LED7)
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#define BOARD_LED8_BIT (1 << BOARD_LED8)
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/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 8 LEDs on board the
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* stm32f3discovery. The following definitions describe how NuttX controls the LEDs:
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*
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* SYMBOL Meaning LED state
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* Initially all LEDs are OFF
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* ------------------- ----------------------- ------------- ------------
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* LED_STARTED NuttX has been started LD3 ON
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* LED_HEAPALLOCATE Heap has been allocated LD4 ON
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* LED_IRQSENABLED Interrupts enabled LD4 ON
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* LED_STACKCREATED Idle stack created LD6 ON
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* LED_INIRQ In an interrupt LD7 should glow
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* LED_SIGNAL In a signal handler LD8 might glow
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* LED_ASSERTION An assertion failed LD9 ON while handling the assertion
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* LED_PANIC The system has crashed LD10 Blinking at 2Hz
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* LED_IDLE STM32 is is sleep mode (Optional, not used)
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*/
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#define LED_STARTED 0
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#define LED_HEAPALLOCATE 1
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#define LED_IRQSENABLED 2
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#define LED_STACKCREATED 3
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#define LED_INIRQ 4
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#define LED_SIGNAL 5
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#define LED_ASSERTION 6
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#define LED_PANIC 7
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/* Button definitions ***************************************************************/
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/* The STM32F3Discovery supports two buttons; only one button is controllable by
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* software:
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*
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* B1 USER: user and wake-up button connected to the I/O PA0 of the STM32F303VCT6.
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* B2 RESET: pushbutton connected to NRST is used to RESET the STM32F303VCT6.
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*/
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#define BUTTON_USER 0
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#define NUM_BUTTONS 1
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#define BUTTON_USER_BIT (1 << BUTTON_USER)
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/* Alternate function pin selections ************************************************/
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/* USART
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*
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* USART1: Hardwired to embedded STLinkV2 hardware debugger
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* RX (PC5)
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* TX (PC4)
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*
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* USART2: Connect to an external UART<->RS232 transceiver for use as console.
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* RX (PA3)
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* TX (PA2)
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*/
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#define GPIO_USART2_RX GPIO_USART2_RX_2
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#define GPIO_USART2_TX GPIO_USART2_TX_2
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/* SPI
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*
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* SPI1: Hardwired to ST L3GD20 MEMS device
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* MISO (PA6)
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* MSOI (PA7)
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* SCK (PA5)
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*/
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#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1
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#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1
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#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1
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/* I2C
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*
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* I2C1: Accessible via expansion headers
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* SCL (PA15)
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* SDA (PA14)
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* SMBA (PB5)
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*
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* I2C2: Accessible via expansion headers
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* SCL (PA9)
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* SDA (PA10)
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* SMBA (PB12)
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*/
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#ifdef CONFIG_STM32_I2C1
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#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1
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#define GPIO_I2C1_SDA GPIO_I2C1_SDA_1
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#endif
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#ifdef CONFIG_STM32_I2C2
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#define GPIO_I2C2_SCL GPIO_I2C2_SCL_1
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#define GPIO_I2C2_SDA GPIO_I2C2_SDA_1
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#endif
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#endif /* __BOARDS_ARM_STM32_STM32F3DISCOVERY_INCLUDE_BOARD_H */
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