3a262416d6
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5146 42af7a65-404d-4744-a932-0658087f49c3
321 lines
18 KiB
C
321 lines
18 KiB
C
/************************************************************************************
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* arch/arm/src/imx/imx_usbd.h
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*
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* Copyright (c) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_IMX_USBD_H
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#define __ARCH_ARM_IMX_USBD_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* USBD Register Offsets ************************************************************/
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#define USBD_FRAME_OFFSET 0x0000
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#define USBD_SPEC_OFFSET 0x0004
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#define USBD_STAT_OFFSET 0x0008
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#define USBD_CTRL_OFFSET 0x000c
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#define USBD_DADR_OFFSET 0x0010
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#define USBD_DDAT_OFFSET 0x0014
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#define USBD_INTR_OFFSET 0x0018
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#define USBD_MASK_OFFSET 0x001c
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#define USBD_ENAB_OFFSET 0x0024
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#define USBD_EP0_OFFSET 0x0030
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#define USBD_EP1_OFFSET 0x0060
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#define USBD_EP2_OFFSET 0x0090
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#define USBD_EP3_OFFSET 0x00c0
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#define USBD_EP4_OFFSET 0x00f0
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#define USBD_EP5_OFFSET 0x0120
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#define USBD_EP_OFFSET(n) (USBD_EP0_OFFSET + (n)*0x0030)
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#define USBD_EP_STAT_OFFSET 0x0000
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#define USBD_EP_INTR_OFFSET 0x0004
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#define USBD_EP_MASK_OFFSET 0x0008
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#define USBD_EP_FDAT_OFFSET 0x000c
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#define USBD_EP_FSTAT_OFFSET 0x0010
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#define USBD_EP_FCTRL_OFFSET 0x0014
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#define USBD_EP_LRFP_OFFSET 0x0018
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#define USBD_EP_LRWP_OFFSET 0x001c
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#define USBD_EP_FALRM_OFFSET 0x0020
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#define USBD_EP_FRDP_OFFSET 0x0024
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#define USBD_EP_FRWP_OFFSET 0x0028
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/* USBD Register Addresses **********************************************************/
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#define IMX_USBD_FRAME (IMX_USBD_VBASE + USBD_FRAME_OFFSET)
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#define IMX_USBD_SPEC (IMX_USBD_VBASE + USBD_SPEC_OFFSET)
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#define IMX_USBD_STAT (IMX_USBD_VBASE + USBD_STAT_OFFSET)
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#define IMX_USBD_CTRL (IMX_USBD_VBASE + USBD_CTRL_OFFSET)
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#define IMX_USBD_DADR (IMX_USBD_VBASE + USBD_DADR_OFFSET)
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#define IMX_USBD_DDAT (IMX_USBD_VBASE + USBD_DDAT_OFFSET)
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#define IMX_USBD_INTR (IMX_USBD_VBASE + USBD_INTR_OFFSET)
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#define IMX_USBD_MASK (IMX_USBD_VBASE + USBD_MASK_OFFSET)
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#define IMX_USBD_ENAB (IMX_USBD_VBASE + USBD_ENAB_OFFSET)
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#define IMX_USBD_EP0_BASE (IMX_USBD_VBASE + USBD_EP0_OFFSET)
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#define IMX_USBD_EP1_BASE (IMX_USBD_VBASE + USBD_EP1_OFFSET)
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#define IMX_USBD_EP2_BASE (IMX_USBD_VBASE + USBD_EP2_OFFSET)
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#define IMX_USBD_EP3_BASE (IMX_USBD_VBASE + USBD_EP3_OFFSET)
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#define IMX_USBD_EP4_BASE (IMX_USBD_VBASE + USBD_EP4_OFFSET)
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#define IMX_USBD_EP5_BASE (IMX_USBD_VBASE + USBD_EP5_OFFSET)
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#define IMX_USBD_EP_BASE(n) (IMX_USBD_VBASE + USBD_EP_OFFSET(n))
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#define IMX_USBD_EP0_STAT (IMX_USBD_EP0_BASE + USBD_EP_STAT_OFFSET)
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#define IMX_USBD_EP0_INTR (IMX_USBD_EP0_BASE + USBD_EP_INTR_OFFSET)
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#define IMX_USBD_EP0_MASK (IMX_USBD_EP0_BASE + USBD_EP_MASK_OFFSET)
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#define IMX_USBD_EP0_FDAT (IMX_USBD_EP0_BASE + USBD_EP_FDAT_OFFSET)
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#define IMX_USBD_EP0_FSTAT (IMX_USBD_EP0_BASE + USBD_EP_FSTAT_OFFSET)
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#define IMX_USBD_EP0_FCTRL (IMX_USBD_EP0_BASE + USBD_EP_FCTRL_OFFSET)
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#define IMX_USBD_EP0_LRFP (IMX_USBD_EP0_BASE + USBD_EP_LRFP_OFFSET)
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#define IMX_USBD_EP0_LRWP (IMX_USBD_EP0_BASE + USBD_EP_LRWP_OFFSET)
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#define IMX_USBD_EP0_FALRM (IMX_USBD_EP0_BASE + USBD_EP_FALRM_OFFSET)
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#define IMX_USBD_EP0_FRDP (IMX_USBD_EP0_BASE + USBD_EP_FRDP_OFFSET)
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#define IMX_USBD_EP0_FRWP (IMX_USBD_EP0_BASE + USBD_EP_FRWP_OFFSET)
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#define IMX_USBD_EP1_STAT (IMX_USBD_EP1_BASE + USBD_EP_STAT_OFFSET)
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#define IMX_USBD_EP1_INTR (IMX_USBD_EP1_BASE + USBD_EP_INTR_OFFSET)
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#define IMX_USBD_EP1_MASK (IMX_USBD_EP1_BASE + USBD_EP_MASK_OFFSET)
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#define IMX_USBD_EP1_FDAT (IMX_USBD_EP1_BASE + USBD_EP_FDAT_OFFSET)
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#define IMX_USBD_EP1_FSTAT (IMX_USBD_EP1_BASE + USBD_EP_FSTAT_OFFSET)
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#define IMX_USBD_EP1_FCTRL (IMX_USBD_EP1_BASE + USBD_EP_FCTRL_OFFSET)
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#define IMX_USBD_EP1_LRFP (IMX_USBD_EP1_BASE + USBD_EP_LRFP_OFFSET)
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#define IMX_USBD_EP1_LRWP (IMX_USBD_EP1_BASE + USBD_EP_LRWP_OFFSET)
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#define IMX_USBD_EP1_FALRM (IMX_USBD_EP1_BASE + USBD_EP_FALRM_OFFSET)
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#define IMX_USBD_EP1_FRDP (IMX_USBD_EP1_BASE + USBD_EP_FRDP_OFFSET)
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#define IMX_USBD_EP1_FRWP (IMX_USBD_EP1_BASE + USBD_EP_FRWP_OFFSET)
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#define IMX_USBD_EP2_STAT (IMX_USBD_EP2_BASE + USBD_EP_STAT_OFFSET)
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#define IMX_USBD_EP2_INTR (IMX_USBD_EP2_BASE + USBD_EP_INTR_OFFSET)
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#define IMX_USBD_EP2_MASK (IMX_USBD_EP2_BASE + USBD_EP_MASK_OFFSET)
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#define IMX_USBD_EP2_FDAT (IMX_USBD_EP2_BASE + USBD_EP_FDAT_OFFSET)
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#define IMX_USBD_EP2_FSTAT (IMX_USBD_EP2_BASE + USBD_EP_FSTAT_OFFSET)
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#define IMX_USBD_EP2_FCTRL (IMX_USBD_EP2_BASE + USBD_EP_FCTRL_OFFSET)
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#define IMX_USBD_EP2_LRFP (IMX_USBD_EP2_BASE + USBD_EP_LRFP_OFFSET)
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#define IMX_USBD_EP2_LRWP (IMX_USBD_EP2_BASE + USBD_EP_LRWP_OFFSET)
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#define IMX_USBD_EP2_FALRM (IMX_USBD_EP2_BASE + USBD_EP_FALRM_OFFSET)
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#define IMX_USBD_EP2_FRDP (IMX_USBD_EP2_BASE + USBD_EP_FRDP_OFFSET)
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#define IMX_USBD_EP2_FRWP (IMX_USBD_EP2_BASE + USBD_EP_FRWP_OFFSET)
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#define IMX_USBD_EP3_STAT (IMX_USBD_EP3_BASE + USBD_EP_STAT_OFFSET)
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#define IMX_USBD_EP3_INTR (IMX_USBD_EP3_BASE + USBD_EP_INTR_OFFSET)
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#define IMX_USBD_EP3_MASK (IMX_USBD_EP3_BASE + USBD_EP_MASK_OFFSET)
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#define IMX_USBD_EP3_FDAT (IMX_USBD_EP3_BASE + USBD_EP_FDAT_OFFSET)
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#define IMX_USBD_EP3_FSTAT (IMX_USBD_EP3_BASE + USBD_EP_FSTAT_OFFSET)
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#define IMX_USBD_EP3_FCTRL (IMX_USBD_EP3_BASE + USBD_EP_FCTRL_OFFSET)
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#define IMX_USBD_EP3_LRFP (IMX_USBD_EP3_BASE + USBD_EP_LRFP_OFFSET)
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#define IMX_USBD_EP3_LRWP (IMX_USBD_EP3_BASE + USBD_EP_LRWP_OFFSET)
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#define IMX_USBD_EP3_FALRM (IMX_USBD_EP3_BASE + USBD_EP_FALRM_OFFSET)
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#define IMX_USBD_EP3_FRDP (IMX_USBD_EP3_BASE + USBD_EP_FRDP_OFFSET)
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#define IMX_USBD_EP3_FRWP (IMX_USBD_EP3_BASE + USBD_EP_FRWP_OFFSET)
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#define IMX_USBD_EP4_STAT (IMX_USBD_EP4_BASE + USBD_EP_STAT_OFFSET)
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#define IMX_USBD_EP4_INTR (IMX_USBD_EP4_BASE + USBD_EP_INTR_OFFSET)
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#define IMX_USBD_EP4_MASK (IMX_USBD_EP4_BASE + USBD_EP_MASK_OFFSET)
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#define IMX_USBD_EP4_FDAT (IMX_USBD_EP4_BASE + USBD_EP_FDAT_OFFSET)
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#define IMX_USBD_EP4_FSTAT (IMX_USBD_EP4_BASE + USBD_EP_FSTAT_OFFSET)
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#define IMX_USBD_EP4_FCTRL (IMX_USBD_EP4_BASE + USBD_EP_FCTRL_OFFSET)
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#define IMX_USBD_EP4_LRFP (IMX_USBD_EP4_BASE + USBD_EP_LRFP_OFFSET)
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#define IMX_USBD_EP4_LRWP (IMX_USBD_EP4_BASE + USBD_EP_LRWP_OFFSET)
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#define IMX_USBD_EP4_FALRM (IMX_USBD_EP4_BASE + USBD_EP_FALRM_OFFSET)
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#define IMX_USBD_EP4_FRDP (IMX_USBD_EP4_BASE + USBD_EP_FRDP_OFFSET)
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#define IMX_USBD_EP4_FRWP (IMX_USBD_EP4_BASE + USBD_EP_FRWP_OFFSET)
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#define IMX_USBD_EP5_STAT (IMX_USBD_EP5_BASE + USBD_EP_STAT_OFFSET)
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#define IMX_USBD_EP5_INTR (IMX_USBD_EP5_BASE + USBD_EP_INTR_OFFSET)
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#define IMX_USBD_EP5_MASK (IMX_USBD_EP5_BASE + USBD_EP_MASK_OFFSET)
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#define IMX_USBD_EP5_FDAT (IMX_USBD_EP5_BASE + USBD_EP_FDAT_OFFSET)
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#define IMX_USBD_EP5_FSTAT (IMX_USBD_EP5_BASE + USBD_EP_FSTAT_OFFSET)
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#define IMX_USBD_EP5_FCTRL (IMX_USBD_EP5_BASE + USBD_EP_FCTRL_OFFSET)
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#define IMX_USBD_EP5_LRFP (IMX_USBD_EP5_BASE + USBD_EP_LRFP_OFFSET)
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#define IMX_USBD_EP5_LRWP (IMX_USBD_EP5_BASE + USBD_EP_LRWP_OFFSET)
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#define IMX_USBD_EP5_FALRM (IMX_USBD_EP5_BASE + USBD_EP_FALRM_OFFSET)
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#define IMX_USBD_EP5_FRDP (IMX_USBD_EP5_BASE + USBD_EP_FRDP_OFFSET)
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#define IMX_USBD_EP5_FRWP (IMX_USBD_EP5_BASE + USBD_EP_FRWP_OFFSET)
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#define IMX_USBD_EP_STAT(n) (IMX_USBD_EP_BASE(n) + USBD_EP_STAT_OFFSET)
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#define IMX_USBD_EP_INTR(n) (IMX_USBD_EP_BASE(n) + USBD_EP_INTR_OFFSET)
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#define IMX_USBD_EP_MASK(n) (IMX_USBD_EP_BASE(n) + USBD_EP_MASK_OFFSET)
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#define IMX_USBD_EP_FDAT(n) (IMX_USBD_EP_BASE(n) + USBD_EP_FDAT_OFFSET)
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#define IMX_USBD_EP_FSTAT(n) (IMX_USBD_EP_BASE(n) + USBD_EP_FSTAT_OFFSET)
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#define IMX_USBD_EP_FCTRL(n) (IMX_USBD_EP_BASE(n) + USBD_EP_FCTRL_OFFSET)
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#define IMX_USBD_EP_LRFP(n) (IMX_USBD_EP_BASE(n) + USBD_EP_LRFP_OFFSET)
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#define IMX_USBD_EP_LRWP(n) (IMX_USBD_EP_BASE(n) + USBD_EP_LRWP_OFFSET)
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#define IMX_USBD_EP_FALRM(n) (IMX_USBD_EP_BASE(n) + USBD_EP_FALRM_OFFSET)
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#define IMX_USBD_EP_FRDP(n) (IMX_USBD_EP_BASE(n) + USBD_EP_FRDP_OFFSET)
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#define IMX_USBD_EP_FRWP(n) (IMX_USBD_EP_BASE(n) + USBD_EP_FRWP_OFFSET)
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/* USBD Register Bit Definitions ****************************************************/
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/* USBD FRAME Register */
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#define USBD_FRAME_FRAME_SHIFT 0 /* Bit 0-10: Frame Field */
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#define USBD_FRAME_FRAME_MASK (0x07ff << USBD_FRAME_FRAME_SHIFT)
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#define USBD_FRAME_MATCH_SHIFT 16 /* Bit 16-26: Match Field */
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#define USBD_FRAME_MATCH_MASK (0x07ff << USBD_FRAME_MATCH_SHIFT)
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/* USBD STAT Register */
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#define USBD_STAT_ALTSET_SHIFT 0 /* Bit 0-2: Alternate Setting */
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#define USBD_STAT_ALTSET_MASK (0x07 << USBD_FRAME_MATCH_SHIFT)
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#define USBD_STAT_INTF_SHIFT 3 /* Bit 3-4: Interface */
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#define USBD_STAT_INTF_MASK (0x03 << USBD_FRAME_MATCH_SHIFT)
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#define USBD_STAT_CFG_SHIFT 5 /* Bit 5-6: Configuration */
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#define USBD_STAT_CFG_MASK (0x03 << USBD_FRAME_MATCH_SHIFT)
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#define USBD_STAT_SUSP (1 << 7) /* Bit 7: Suspend */
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#define USBD_STAT_RST (1 << 8) /* Bit 8: Reset Signaling */
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/* USBD CTRL Register */
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#define USBD_CTRL_RESUME (1 << 0) /* Bit 0: Resume */
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#define USBD_CTRL_AFEENA (1 << 1) /* Bit 1: Analog Front-End Enable */
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#define USBD_CTRL_UDCRST (1 << 2) /* Bit 2: UDC Reset */
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#define USBD_CTRL_USBENA (1 << 3) /* Bit 3: USB Enable */
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#define USBD_CTRL_USBSPD (1 << 4) /* Bit 4: USB Speed */
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#define USBD_CTRL_CMDERROR (1 << 5) /* Bit 5: Command Error */
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#define USBD_CTRL_CMDOVER (1 << 6) /* Bit 6: Command Over */
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/* USBD DADR Register */
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#define USBD_DADR_DADR_SHIFT 0 /* Bit 0-8: Desired RAM Address */
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#define USBD_DADR_DADR_MASK (0x1ff << USBD_DADR_DADR_SHIFT)
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#define USBD_DADR_BSY (1 << 30) /* Bit 30: Busy */
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#define USBD_DADR_CFG (1 << 31) /* Bit 31: Configuration */
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/* USBD DDAT Register */
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#define USBD_DDAT_DDAT_SHIFT 0 /* Bit 0-7: Descriptor Data Buffer */
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#define USBD_DDAT_DDAT_MASK (0xff << USBD_DDAT_DDAT_SHIFT)
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/* USBD INTR Register */
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#define USBD_INTR_CFGCHG (1 << 0) /* Bit 0: Configuration Change */
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#define USBD_INTR_FRAMEMATCH (1 << 1) /* Bit 1: FRAME_MATCH */
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#define USBD_INTR_SUSP (1 << 2) /* Bit 2: Active to Suspend */
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#define USBD_INTR_RES (1 << 3) /* Bit 3: Suspend to Resume */
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#define USBD_INTR_RESETSTART (1 << 4) /* Bit 4: Restart Signaling Start */
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#define USBD_INTR_RESETSTOP (1 << 5) /* Bit 5: Restart Signaling Stop */
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#define USBD_INTR_SOF (1 << 6) /* Bit 6: Start-of-Frame Interrupt */
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#define USBD_INTR_MSOF (1 << 7) /* Bit 7: Missed Start-of-Frame Interrupt */
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#define USBD_INTR_WAKEUP (1 << 31) /* Bit 31: Wakeup */
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/* USBD MASK Register */
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#define USBD_MASK_CFGCHG (1 << 0) /* Bit 0: Configuration Change */
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#define USBD_MASK_FRAMEMATCH (1 << 1) /* Bit 1: FRAME_MATCH */
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#define USBD_MASK_SUSP (1 << 2) /* Bit 2: Active to Suspend */
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#define USBD_MASK_RES (1 << 3) /* Bit 3: Suspend to Resume */
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#define USBD_MASK_RESETSTART (1 << 4) /* Bit 4: Restart Signaling Start */
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#define USBD_MASK_RESETSTOP (1 << 5) /* Bit 5: Restart Signaling Stop */
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#define USBD_MASK_SOF (1 << 6) /* Bit 6: Start-of-Frame Interrupt */
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#define USBD_MASK_MSOF (1 << 7) /* Bit 7: Missed Start-of-Frame Interrupt */
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#define USBD_MASK_WAKEUP (1 << 31) /* Bit 31: Wakeup */
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/* USBD ENAB Register */
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#define USBD_ENAB_PWDMD (1 << 0) /* Bit 0: Power Mode */
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#define USBD_ENAB_ENDIANMODE (1 << 28) /* Bit 28: Endian Mode Select */
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#define USBD_ENAB_SUSPEND (1 << 29) /* Bit 29: Suspend */
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#define USBD_ENAB_ENAB (1 << 30) /* Bit 30: Enable */
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#define USBD_ENAB_RST (1 << 31) /* Bit 31: Reset */
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/* USBD EPSTAT Register */
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#define USBD_EPSTAT_FORCESTALL (1 << 0) /* Bit 0: Force a Stall Condition */
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#define USBD_EPSTAT_FLUSH (1 << 1) /* Bit 1: Flush */
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#define USBD_EPSTAT_ZLPS (1 << 2) /* Bit 2: Zero Length Packet Send */
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#define USBD_EPSTAT_TYP_SHIFT 3 /* Bit 3-4: Endpoint Type */
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#define USBD_EPSTAT_TYP_MASK (0x03 << USBD_EPSTAT_TYP_SHIFT)
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#define USBD_EPSTAT_MAX_SHIFT 5 /* Bit 5-6: Maximum Packet Size */
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#define USBD_EPSTAT_MAX_MASK (0x03 << USBD_EPSTAT_MAX_SHIFT)
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#define USBD_EPSTAT_DIR (1 << 7) /* Bit 7: Transfer Direction */
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#define USBD_EPSTAT_SIP (1 << 8) /* Bit 8: Setup Packet in Progress */
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#define USBD_EPSTAT_BYTECOUNT_SHIFT 16 /* Bit 16-22: Byte Count */
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#define USBD_EPSTAT_BYTECOUNT_MASK (0x7f << USBD_EPSTAT_BYTECOUNT_SHIFT)
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/* USBD EPINTR Register */
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#define USBD_EPINTR_EOF (1 << 0) /* Bit 0: End-of-Frame */
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#define USBD_EPINTR_DEVREQ (1 << 1) /* Bit 1: Device Request */
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#define USBD_EPINTR_EOT (1 << 2) /* Bit 2: End of Transfer */
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#define USBD_EPINTR_MDEVREQ (1 << 3) /* Bit 3: Multiple Device Request */
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#define USBD_EPINTR_FIFOLOW (1 << 4) /* Bit 4: FIFO Low */
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#define USBD_EPINTR_FIFOHIGH (1 << 5) /* Bit 5: FIFO High */
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#define USBD_EPINTR_FIFOERROR (1 << 6) /* Bit 6: FIFO Error */
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#define USBD_EPINTR_FIFOEMPTY (1 << 7) /* Bit 7: FIFO Empty */
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#define USBD_EPINTR_FIFOFULL (1 << 8) /* Bit 8: FIFO Full */
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/* USBD EPMASK Register */
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#define USBD_EPMASK_EOF (1 << 0) /* Bit 0: End-of-Frame */
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#define USBD_EPMASK_DEVREQ (1 << 1) /* Bit 1: Device Request */
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#define USBD_EPMASK_EOT (1 << 2) /* Bit 2: End of Transfer */
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#define USBD_EPMASK_MDEVREQ (1 << 3) /* Bit 3: Multiple Device Request */
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#define USBD_EPMASK_FIFOLOW (1 << 4) /* Bit 4: FIFO Low */
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#define USBD_EPMASK_FIFOHIGH (1 << 5) /* Bit 5: FIFO High */
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#define USBD_EPMASK_FIFOERROR (1 << 6) /* Bit 6: FIFO Error */
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#define USBD_EPMASK_FIFOEMPTY (1 << 7) /* Bit 7: FIFO Empty */
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#define USBD_EPMASK_FIFOFULL (1 << 8) /* Bit 8: FIFO Full */
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/* USBD EPFSTAT Register */
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#define USBD_EPFSTAT_EMPTY (1 << 16) /* Bit 16: FIFO Empty */
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#define USBD_EPFSTAT_ALARM (1 << 17) /* Bit 17: FIFO Alarm */
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#define USBD_EPFSTAT_FULL (1 << 18) /* Bit 18: FIFO Full */
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#define USBD_EPFSTAT_FR (1 << 19) /* Bit 19: FIFO Ready */
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#define USBD_EPFSTAT_OF (1 << 20) /* Bit 20: FIFO Overflow */
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#define USBD_EPFSTAT_UF (1 << 21) /* Bit 21: FIFO Underflow */
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#define USBD_EPFSTAT_ERROR (1 << 22) /* Bit 22: FIFO Error */
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#define USBD_EPFSTAT_FRAME3 (1 << 24) /* Bit 24: Frame Status Bit 3 */
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#define USBD_EPFSTAT_FRAME2 (1 << 25) /* Bit 25: Frame Status Bit 2 */
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#define USBD_EPFSTAT_FRAME1 (1 << 26) /* Bit 26: Frame Status Bit 1 */
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#define USBD_EPFSTAT_FRAME0 (1 << 27) /* Bit 27: Frame Status Bit 0 */
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/* USBD EPFCTRL Register */
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#define USBD_EPCTRL_GR_SHIFT 24 /* Bit 24-26: Granularity */
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#define USBD_EPCTRL_GR_MASK (0x07 << USBD_EPCTRL_GR_SHIFT)
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#define USBD_EPCTRL_FRAME (1 << 27) /* Bit 27: Frame Mode */
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#define USBD_EPCTRL_WFR (1 << 28) /* Bit 29: Write Frame End */
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/************************************************************************************
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* Inline Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_IMX_USBD_H */
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