615 lines
19 KiB
C
615 lines
19 KiB
C
/****************************************************************************
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* arch/arm/src/lpc17xx_40xx/lpc17_40_timer.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <assert.h>
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#include <errno.h>
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#include <debug.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <nuttx/timers/pwm.h>
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#include <arch/board/board.h>
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#include "arm_internal.h"
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#include "arm_arch.h"
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#include "chip.h"
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#include "hardware/lpc17_40_syscon.h"
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#include "lpc17_40_timer.h"
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#include "hardware/lpc176x_pinconfig.h"
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#include "lpc17_40_gpio.h"
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#include "lpc176x_gpio.h"
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/* This module then only compiles if there is at least one enabled timer
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* intended for use with the TIMER upper half driver.
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*/
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#if defined(CONFIG_LPC17_40_TMR0)
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* PWM/Timer Definitions ****************************************************/
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/* The following definitions are used to identify the various time types */
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#define TIMTYPE_BASIC 0 /* Basic timers: TIM6-7 */
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#define TIMTYPE_GENERAL16 1 /* General 16-bit timers: TIM2-5 on F1 */
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#define TIMTYPE_COUNTUP16 2 /* General 16-bit count-up timers: TIM9-14 on F4 */
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#define TIMTYPE_GENERAL32 3 /* General 32-bit timers: TIM2-5 on F4 */
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#define TIMTYPE_ADVANCED 4 /* Advanced timers: TIM1-8 */
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#define TIMTYPE_TIM1 TIMTYPE_ADVANCED
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/* Debug ********************************************************************/
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#ifdef CONFIG_DEBUG_PWM_INFO
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# define pwm_dumpgpio(p,m) stm32_dumpgpio(p,m)
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#else
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# define pwm_dumpgpio(p,m)
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#endif
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/* This structure represents the state of one PWM timer */
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struct lpc17_40_timer_s
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{
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FAR const struct pwm_ops_s *ops; /* PWM operations */
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uint8_t timid; /* Timer ID {0,...,7} */
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uint8_t channel; /* Timer output channel: {1,..4} */
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uint8_t timtype; /* See the TIMTYPE_* definitions */
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uint32_t base; /* The base address of the timer */
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uint32_t pincfg; /* Output pin configuration */
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uint32_t pclk; /* The frequency of the peripheral clock
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* that drives the timer module. */
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};
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/****************************************************************************
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* Static Function Prototypes
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****************************************************************************/
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/* Register access */
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static uint32_t timer_getreg(struct lpc17_40_timer_s *priv, int offset);
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static void timer_putreg(struct lpc17_40_timer_s *priv,
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int offset, uint32_t value);
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#ifdef CONFIG_DEBUG_PWM_INFO
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static void timer_dumpregs(struct lpc17_40_timer_s *priv,
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FAR const char *msg);
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#else
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# define timer_dumpregs(priv,msg)
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#endif
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/* Timer management */
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static int timer_timer(FAR struct lpc17_40_timer_s *priv,
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FAR const struct pwm_info_s *info);
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/* PWM driver methods */
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static int timer_setup(FAR struct pwm_lowerhalf_s *dev);
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static int timer_shutdown(FAR struct pwm_lowerhalf_s *dev);
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static int timer_start(FAR struct pwm_lowerhalf_s *dev,
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FAR const struct pwm_info_s *info);
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static int timer_stop(FAR struct pwm_lowerhalf_s *dev);
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static int timer_ioctl(FAR struct pwm_lowerhalf_s *dev,
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int cmd, unsigned long arg);
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* This is the list of lower half PWM driver methods used by the upper half
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* driver
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*/
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static const struct pwm_ops_s g_pwmops =
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{
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.setup = timer_setup,
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.shutdown = timer_shutdown,
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.start = timer_start,
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.stop = timer_stop,
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.ioctl = timer_ioctl,
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};
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#ifdef CONFIG_LPC17_40_TMR0
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static struct lpc17_40_timer_s g_pwm1dev =
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{
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.ops = &g_pwmops,
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.timid = 1,
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.channel = CONFIG_LPC17_40_MAT0_PIN,
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.timtype = TIMTYPE_TIM1,
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.base = LPC17_40_TMR1_BASE,
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.pincfg = GPIO_MAT0p1_2,
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.pclk = (0x1 << 12),
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};
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#endif
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: timer_getreg
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*
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* Description:
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* Read the value of an PWM timer register.
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*
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* Input Parameters:
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* priv - A reference to the PWM block status
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* offset - The offset to the register to read
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*
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* Returned Value:
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* The current contents of the specified register
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*
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****************************************************************************/
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static uint32_t timer_getreg(struct lpc17_40_timer_s *priv, int offset)
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{
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return getreg32(priv->base + offset);
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}
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/****************************************************************************
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* Name: timer_putreg
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*
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* Description:
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* Read the value of an PWM timer register.
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*
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* Input Parameters:
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* priv - A reference to the PWM block status
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* offset - The offset to the register to read
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static void timer_putreg(struct lpc17_40_timer_s *priv, int offset,
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uint32_t value)
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{
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putreg32(value, priv->base + offset);
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}
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/****************************************************************************
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* Name: timer_dumpregs
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*
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* Description:
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* Dump all timer registers.
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*
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* Input Parameters:
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* priv - A reference to the PWM block status
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#ifdef CONFIG_DEBUG_PWM_INFO
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static void timer_dumpregs(struct lpc17_40_timer_s *priv,
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FAR const char *msg)
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{
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pwminfo("%s:\n", msg);
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pwminfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
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timer_getreg(priv, LPC17_40_PWM_MR0_OFFSET),
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timer_getreg(priv, LPC17_40_PWM_MR1_OFFSET),
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timer_getreg(priv, LPC17_40_PWM_MR2_OFFSET),
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timer_getreg(priv, LPC17_40_PWM_MR3_OFFSET));
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#if defined(CONFIG_LPC17_40_TMR0)
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if (priv->timtype == TIMTYPE_ADVANCED)
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{
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pwminfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
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timer_getreg(priv, LPC17_40_PWM_MR0_OFFSET),
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timer_getreg(priv, LPC17_40_PWM_MR1_OFFSET),
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timer_getreg(priv, LPC17_40_PWM_MR2_OFFSET),
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timer_getreg(priv, LPC17_40_PWM_MR3_OFFSET));
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}
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else
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#endif
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{
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pwminfo(" DCR: %04x DMAR: %04x\n",
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timer_getreg(priv, LPC17_40_PWM_MR2_OFFSET),
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timer_getreg(priv, LPC17_40_PWM_MR3_OFFSET));
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}
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}
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#endif
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/****************************************************************************
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* Name: timer_timer
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*
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* Description:
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* (Re-)initialize the timer resources and start the pulsed output
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*
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* Input Parameters:
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* priv - A reference to the lower half PWM driver state structure
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* info - A reference to the characteristics of the pulsed output
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure
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*
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****************************************************************************/
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static int timer_timer(FAR struct lpc17_40_timer_s *priv,
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FAR const struct pwm_info_s *info)
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{
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irqstate_t flags;
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uint32_t regval;
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flags = enter_critical_section();
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putreg32(info->frequency, LPC17_40_TMR0_MR1); /* Set TIMER0 MR1 = number of counts */
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putreg32(info->frequency, LPC17_40_TMR1_MR0); /* Set TIMER1 MR0 = number of counts */
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putreg32(1, LPC17_40_TMR0_TCR); /* Start timer0 */
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putreg32(1, LPC17_40_TMR1_TCR); /* Start timer1 */
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leave_critical_section(flags);
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timer_dumpregs(priv, "After starting");
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return OK;
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}
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#ifdef XXXXX
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/****************************************************************************
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* Name: timer_interrupt
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*
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* Description:
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* Handle timer interrupts.
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*
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* Input Parameters:
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* priv - A reference to the lower half PWM driver state structure
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure
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*
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****************************************************************************/
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static int timer_interrupt(struct lpc17_40_timer_s *priv)
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{
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uint16_t regval;
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/* Verify that this is an update interrupt. Nothing else is expected. */
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regval = timer_getreg(priv, STM32_ATIM_SR_OFFSET);
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DEBUGASSERT((regval & ATIM_SR_UIF) != 0);
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/* Clear the UIF interrupt bit */
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timer_putreg(priv, STM32_ATIM_SR_OFFSET, regval & ~ATIM_SR_UIF);
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/* Calculate the new count by subtracting the number of pulses
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* since the last interrupt.
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*/
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return OK;
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}
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/****************************************************************************
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* Name: timer_tim1/8interrupt
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*
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* Description:
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* Handle timer 1 and 8 interrupts.
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*
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* Input Parameters:
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* Standard NuttX interrupt inputs
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure
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*
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****************************************************************************/
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static int timer_tim1interrupt(int irq, void *context)
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{
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return timer_interrupt(&g_pwm1dev);
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}
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#endif /* XXXXX */
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/****************************************************************************
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* Name: timer_setup
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*
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* Description:
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* This method is called when the driver is opened. The lower half driver
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* should configure and initialize the device so that it is ready for use.
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* It should not, however, output pulses until the start method is called.
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*
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* Input Parameters:
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* dev - A reference to the lower half PWM driver state structure
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure
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*
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* Assumptions:
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* APB1 or 2 clocking for the GPIOs has already been configured by the RCC
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* logic at power up.
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*
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****************************************************************************/
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static int timer_setup(FAR struct pwm_lowerhalf_s *dev)
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{
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FAR struct lpc17_40_timer_s *priv = (FAR struct lpc17_40_timer_s *)dev;
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irqstate_t flags;
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uint32_t regval;
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flags = enter_critical_section();
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/* Power on the timer peripherals */
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regval = getreg32(LPC17_40_SYSCON_PCONP);
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regval |= SYSCON_PCONP_PCTIM0;
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regval |= SYSCON_PCONP_PCTIM1;
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regval |= SYSCON_PCONP_PCTIM2;
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regval |= SYSCON_PCONP_PCTIM3;
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putreg32(regval, LPC17_40_SYSCON_PCONP);
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/* Select clock for the timer peripheral */
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regval = getreg32(LPC17_40_SYSCON_PCLKSEL0);
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regval &= ~(0x3 << 2);
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regval |= (0x1 << 2); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */
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regval &= ~(0x3 << 4);
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regval |= (0x1 << 4); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */
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putreg32(regval, LPC17_40_SYSCON_PCLKSEL0);
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regval = getreg32(LPC17_40_SYSCON_PCLKSEL1);
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regval &= ~(0x3 << 12);
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regval |= (0x1 << 12); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */
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regval &= ~(0x3 << 14);
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regval |= (0x1 << 14); /* PCLK_MC peripheral clk=CCLK=12.5 MHz */
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putreg32(regval, LPC17_40_SYSCON_PCLKSEL1);
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priv->pclk = (0x1 << 12) | (0x1 << 4);
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putreg32(1000, LPC17_40_TMR0_MR1); /* Set TIMER0 MR1 = number of counts */
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putreg32(1, LPC17_40_TMR0_PR); /* Prescaler count frequency: Fpclk/1 */
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putreg32(~(0x3 << 0), LPC17_40_TMR0_CCR); /* Prescaler count frequency: Fpclk/1 */
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putreg32(~(0x3 << 0), LPC17_40_TMR0_CTCR); /* Prescaler count frequency: Fpclk/1 */
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putreg32((2 << 3), LPC17_40_TMR0_MCR); /* Reset on match register MR1 */
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/* Output bit toggle on external match event External match on MR1, Toggle
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* external bit
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*/
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putreg32(((1 << 1) | (3 << 6)), LPC17_40_TMR0_EMR);
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putreg32((1 << 0), LPC17_40_TMR0_TCR); /* Start timer0 */
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/* Configure the output pins GPIO3.26 */
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lpc17_40_configgpio(GPIO_MAT0p1_2);
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putreg32(500, LPC17_40_TMR1_MR0); /* Set TIMER1 MR0 = number of counts */
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putreg32(1, LPC17_40_TMR1_PR); /* Prescaler count frequency:Fpclk/1 */
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putreg32(~(0x3 << 0), LPC17_40_TMR1_CCR); /* Prescaler count frequency:Fpclk/1 */
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putreg32(~(0x3 << 0), LPC17_40_TMR1_CTCR); /* Prescaler count frequency:Fpclk/1 */
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putreg32((2 << 0), LPC17_40_TMR1_MCR); /* Reset on match register MR0 */
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/* putreg32(((1 << 0 )| (3 << 4)), LPC17_40_TMR1_EMR);
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* Output bit toggle on external match event MAT0
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*/
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putreg32((1 << 0), LPC17_40_TMR1_TCR); /* Start timer1 */
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/* configure the output pins GPIO3.26 */
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/* lpc17_40_configgpio(GPIO_MAT0p1_2); */
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leave_critical_section(flags);
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pwm_dumpgpio(priv->pincfg, "TIMER setup");
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return OK;
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}
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/****************************************************************************
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* Name: timer_shutdown
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*
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* Description:
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* This method is called when the driver is closed. The lower half driver
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* stop pulsed output, free any resources, disable the timer hardware, and
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* put the system into the lowest possible power usage state
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*
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* Input Parameters:
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* dev - A reference to the lower half TIMER driver state structure
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure
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*
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****************************************************************************/
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static int timer_shutdown(FAR struct pwm_lowerhalf_s *dev)
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{
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FAR struct lpc17_40_timer_s *priv = (FAR struct lpc17_40_timer_s *)dev;
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uint32_t pincfg;
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pwminfo("TIM%d pincfg: %08x\n", priv->timid, priv->pincfg);
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/* Make sure that the output has been stopped */
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return OK;
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}
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/****************************************************************************
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* Name: timer_start
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*
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* Description:
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* (Re-)initialize the timer resources and start the pulsed output
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*
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* Input Parameters:
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* dev - A reference to the lower half TIMER driver state structure
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* info - A reference to the characteristics of the pulsed output
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure
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*
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****************************************************************************/
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static int timer_start(FAR struct pwm_lowerhalf_s *dev,
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FAR const struct pwm_info_s *info)
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{
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FAR struct lpc17_40_timer_s *priv = (FAR struct lpc17_40_timer_s *)dev;
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return timer_timer(priv, info);
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}
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/****************************************************************************
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* Name: timer_stop
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*
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* Description:
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* Stop the pulsed output and reset the timer resources
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*
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* Input Parameters:
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* dev - A reference to the lower half TIMER driver state structure
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure
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*
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* Assumptions:
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* This function is called to stop the pulsed output at anytime. This
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* method is also called from the timer interrupt handler when a repetition
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* count expires... automatically stopping the timer.
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*
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****************************************************************************/
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static int timer_stop(FAR struct pwm_lowerhalf_s *dev)
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{
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FAR struct lpc17_40_timer_s *priv = (FAR struct lpc17_40_timer_s *)dev;
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uint32_t resetbit;
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uint32_t regaddr;
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uint32_t regval;
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irqstate_t flags;
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pwminfo("TIM%d\n", priv->timid);
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/* Disable interrupts momentary to stop any ongoing timer processing and
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* to prevent any concurrent access to the reset register.
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*/
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flags = enter_critical_section();
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/* Disable further interrupts and stop the timer */
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|
|
/* Determine which timer to reset */
|
|
|
|
switch (priv->timid)
|
|
{
|
|
#ifdef CONFIG_LPC17_40_TMR0
|
|
case 1:
|
|
break;
|
|
#endif
|
|
}
|
|
|
|
/* Reset the timer - stopping the output and putting the timer back
|
|
* into a state where timer_start() can be called.
|
|
*/
|
|
|
|
leave_critical_section(flags);
|
|
|
|
pwminfo("regaddr: %08x resetbit: %08x\n", regaddr, resetbit);
|
|
timer_dumpregs(priv, "After stop");
|
|
return OK;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: timer_ioctl
|
|
*
|
|
* Description:
|
|
* Lower-half logic may support platform-specific ioctl commands
|
|
*
|
|
* Input Parameters:
|
|
* dev - A reference to the lower half TIMER driver state structure
|
|
* cmd - The ioctl command
|
|
* arg - The argument accompanying the ioctl command
|
|
*
|
|
* Returned Value:
|
|
* Zero on success; a negated errno value on failure
|
|
*
|
|
****************************************************************************/
|
|
|
|
static int timer_ioctl(FAR struct pwm_lowerhalf_s *dev,
|
|
int cmd, unsigned long arg)
|
|
{
|
|
#ifdef CONFIG_DEBUG_PWM_INFO
|
|
FAR struct lpc17_40_timer_s *priv = (FAR struct lpc17_40_timer_s *)dev;
|
|
|
|
/* There are no platform-specific ioctl commands */
|
|
|
|
pwminfo("TIM%d\n", priv->timid);
|
|
#endif
|
|
return -ENOTTY;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Public Functions
|
|
****************************************************************************/
|
|
|
|
/****************************************************************************
|
|
* Name: lpc17_40_timerinitialize
|
|
*
|
|
* Description:
|
|
* Initialize one timer for use with the upper_level TIMER driver.
|
|
*
|
|
* Input Parameters:
|
|
* timer - A number identifying the timer use. The number of valid timer
|
|
* IDs varies with the STM32 MCU and MCU family but is somewhere in
|
|
* the range of {1,..,14}.
|
|
*
|
|
* Returned Value:
|
|
* On success, a pointer to the STM32 lower half TIMER driver is returned.
|
|
* NULL is returned on any failure.
|
|
*
|
|
****************************************************************************/
|
|
|
|
FAR struct pwm_lowerhalf_s *lpc17_40_timerinitialize(int timer)
|
|
{
|
|
FAR struct lpc17_40_timer_s *lower;
|
|
|
|
pwminfo("TIM%d\n", timer);
|
|
|
|
switch (timer)
|
|
{
|
|
#ifdef CONFIG_LPC17_40_TMR0
|
|
case 0:
|
|
lower = &g_pwm1dev;
|
|
|
|
/* Attach but disable the TIM1 update interrupt */
|
|
|
|
break;
|
|
#endif
|
|
|
|
default:
|
|
pwmerr("ERROR: No such timer configured\n");
|
|
return NULL;
|
|
}
|
|
|
|
return (FAR struct pwm_lowerhalf_s *)lower;
|
|
}
|
|
|
|
#endif /* CONFIG_LPC17_40_TIMn_TIMER, n = 1,...,14 */
|