de435a8a1e
Gregory Nutt has submitted the SGA and we can migrate the licenses to Apache. Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
338 lines
10 KiB
C
338 lines
10 KiB
C
/****************************************************************************
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* arch/arm/src/efm32/efm32_start.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <assert.h>
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#include <debug.h>
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#include <nuttx/init.h>
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#include <nuttx/syslog/syslog.h>
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#include <arch/board/board.h>
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#include <arch/efm32/chip.h>
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#include "arm_arch.h"
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#include "arm_internal.h"
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#include "efm32_config.h"
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#include "efm32_lowputc.h"
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#include "efm32_clockconfig.h"
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#include "efm32_start.h"
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#include "nvic.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* .data is positioned first in the primary RAM followed immediately by .bss.
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* The IDLE thread stack lies just after .bss and has size give by
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* CONFIG_IDLETHREAD_STACKSIZE; The heap then begins just after the IDLE
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* ARM EABI requires 64 bit stack alignment.
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*/
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#define IDLE_STACKSIZE (CONFIG_IDLETHREAD_STACKSIZE & ~7)
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#define IDLE_STACK ((uintptr_t)&_ebss + IDLE_STACKSIZE)
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#define HEAP_BASE ((uintptr_t)&_ebss + IDLE_STACKSIZE)
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/* g_idle_topstack: _sbss is the start of the BSS region as defined by the
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* linker script. _ebss lies at the end of the BSS region. The idle task
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* stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.
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* The IDLE thread is the thread that the system boots on and, eventually,
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* becomes the IDLE, do nothing task that runs only when there is nothing
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* else to run. The heap continues from there until the end of memory.
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* g_idle_topstack is a read-only variable the provides this computed
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* address.
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*/
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const uintptr_t g_idle_topstack = HEAP_BASE;
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/****************************************************************************
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* Private Function prototypes
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****************************************************************************/
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#ifdef CONFIG_ARCH_FPU
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static inline void efm32_fpuconfig(void);
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#endif
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#ifdef CONFIG_STACK_COLORATION
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static void go_nx_start(void *pv, unsigned int nbytes)
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__attribute__ ((naked, no_instrument_function, noreturn));
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#endif
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: showprogress
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*
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* Description:
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* Print a character on the UART to show boot status.
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*
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****************************************************************************/
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#ifdef CONFIG_DEBUG_FEATURES
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# if defined(CONFIG_ARMV7M_ITMSYSLOG)
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# define showprogress(c) (void)syslog_putc(c)
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# elif defined(HAVE_UART_CONSOLE) || defined(HAVE_LEUART_CONSOLE)
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# define showprogress(c) efm32_lowputc(c)
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# else
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# define showprogress(c)
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# endif
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#else
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# define showprogress(c)
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#endif
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/****************************************************************************
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* Name: efm32_fpuconfig
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*
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* Description:
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* Configure the FPU. Relative bit settings:
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*
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* CPACR: Enables access to CP10 and CP11
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* CONTROL.FPCA: Determines whether the FP extension is active in the
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* current context:
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* FPCCR.ASPEN: Enables automatic FP state preservation, then the
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* processor sets this bit to 1 on successful completion of any FP
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* instruction.
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* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
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* done, the processor reserves space on the stack for the FP state,
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* but does not save that state information to the stack.
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*
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* Software must not change the value of the ASPEN bit or LSPEN bit either:
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* - the CPACR permits access to CP10 and CP11, that give access to the FP
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* extension, or
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* - the CONTROL.FPCA bit is set to 1
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*
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****************************************************************************/
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#ifdef CONFIG_ARCH_FPU
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#ifndef CONFIG_ARMV7M_LAZYFPU
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static inline void efm32_fpuconfig(void)
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{
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uint32_t regval;
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/* Set CONTROL.FPCA so that we always get the extended context frame
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* with the volatile FP registers stacked above the basic context.
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*/
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regval = getcontrol();
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regval |= (1 << 2);
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setcontrol(regval);
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/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
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* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
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* are going to turn on CONTROL.FPCA for all contexts.
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*/
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regval = getreg32(NVIC_FPCCR);
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regval &= ~((1 << 31) | (1 << 30));
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putreg32(regval, NVIC_FPCCR);
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/* Enable full access to CP10 and CP11 */
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regval = getreg32(NVIC_CPACR);
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regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
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putreg32(regval, NVIC_CPACR);
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}
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#else
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static inline void efm32_fpuconfig(void)
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{
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uint32_t regval;
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/* Clear CONTROL.FPCA so that we do not get the extended context frame
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* with the volatile FP registers stacked in the saved context.
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*/
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regval = getcontrol();
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regval &= ~(1 << 2);
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setcontrol(regval);
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/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
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* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
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* are going to keep CONTROL.FPCA off for all contexts.
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*/
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regval = getreg32(NVIC_FPCCR);
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regval &= ~((1 << 31) | (1 << 30));
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putreg32(regval, NVIC_FPCCR);
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/* Enable full access to CP10 and CP11 */
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regval = getreg32(NVIC_CPACR);
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regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
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putreg32(regval, NVIC_CPACR);
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}
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#endif
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#else
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# define efm32_fpuconfig()
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#endif
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/****************************************************************************
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* Name: go_nx_start
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*
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* Description:
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* Set the IDLE stack to the coloration value and jump into nx_start()
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*
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****************************************************************************/
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#ifdef CONFIG_STACK_COLORATION
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static void go_nx_start(void *pv, unsigned int nbytes)
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{
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/* Set the IDLE stack to the stack coloration value then jump to
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* nx_start(). We take extreme care here because were currently
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* executing on this stack.
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*
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* We want to avoid sneak stack access generated by the compiler.
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*/
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__asm__ __volatile__
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(
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"\tmovs r1, r1, lsr #2\n" /* R1 = nwords = nbytes >> 2 */
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"\tcmp r1, #0\n" /* Check (nwords == 0) */
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"\tbeq 2f\n" /* (should not happen) */
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"\tbic r0, r0, #3\n" /* R0 = Aligned stackptr */
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"\tmovw r2, #0xbeef\n" /* R2 = STACK_COLOR = 0xdeadbeef */
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"\tmovt r2, #0xdead\n"
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"1:\n" /* Top of the loop */
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"\tsub r1, r1, #1\n" /* R1 nwords-- */
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"\tcmp r1, #0\n" /* Check (nwords == 0) */
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"\tstr r2, [r0], #4\n" /* Save stack color word, increment stackptr */
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"\tbne 1b\n" /* Bottom of the loop */
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"2:\n"
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"\tmov r14, #0\n" /* LR = return address (none) */
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"\tb nx_start\n" /* Branch to nx_start */
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);
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}
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: _start
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*
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* Description:
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* This is the reset entry point.
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*
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****************************************************************************/
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void __start(void)
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{
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const uint32_t *src;
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uint32_t *dest;
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/* Configure the uart so that we can get debug output as soon as possible */
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efm32_clockconfig();
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efm32_fpuconfig();
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efm32_lowsetup();
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showprogress('A');
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/* Clear .bss. We'll do this inline (vs. calling memset) just to be
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* certain that there are no issues with the state of global variables.
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*/
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for (dest = &_sbss; dest < &_ebss; )
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{
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*dest++ = 0;
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}
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showprogress('B');
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/* Move the initialized data section from his temporary holding spot in
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* FLASH into the correct place in SRAM. The correct place in SRAM is
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* give by _sdata and _edata. The temporary location is in FLASH at the
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* end of all of the other read-only data (.text, .rodata) at _eronly.
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*/
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for (src = &_eronly, dest = &_sdata; dest < &_edata; )
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{
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*dest++ = *src++;
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}
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showprogress('C');
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#ifdef CONFIG_ARMV7M_ITMSYSLOG
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/* Perform ARMv7-M ITM SYSLOG initialization */
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itm_syslog_initialize();
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#endif
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/* Perform early serial initialization */
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arm_earlyserialinit();
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showprogress('D');
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/* For the case of the separate user-/kernel-space build, perform whatever
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* platform specific initialization of the user memory is required.
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* Normally this just means initializing the user space .data and .bss
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* segments.
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*/
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#ifdef CONFIG_NUTTX_KERNEL
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efm32_userspace();
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showprogress('E');
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#endif
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/* Initialize onboard resources */
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efm32_boardinitialize();
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showprogress('F');
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/* Then start NuttX */
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showprogress('\r');
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showprogress('\n');
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#ifdef CONFIG_STACK_COLORATION
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/* Set the IDLE stack to the coloration value and jump into nx_start() */
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go_nx_start((FAR void *)&_ebss, CONFIG_IDLETHREAD_STACKSIZE);
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#else
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/* Call nx_start() */
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nx_start();
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/* Shouldn't get here */
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for (; ; );
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#endif
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}
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