de47c8f52f
arm: codestyle fixes 3
* arm: lpc214x: codestyle fixes
After the board restructuration is time for codestyle cleanup
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arm: lpc2378: codestyle fixes
After the board restructuration is time for codestyle cleanup
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arm: lpc31xx: codestyle fixes
After the board restructuration is time for codestyle cleanup
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arm: lpc54xx: codestyle fixes
After the board restructuration is time for codestyle cleanup
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arm: lpc43xx: codestyle fixes
After the board restructuration is time for codestyle cleanup
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
118 lines
5.2 KiB
C
118 lines
5.2 KiB
C
/****************************************************************************
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* boards/arm/lpc31xx/ea3131/include/board.h
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* include/arch/board/board.h
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*
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* Copyright (C) 2009-2010, 2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_LPC31XX_EA3131_INCLUDE_BOARD_H
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#define __BOARDS_ARM_LPC31XX_EA3131_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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# include "lpc31_cgudrvr.h"
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* Frequency of the FFAST input */
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#define BOARD_FREQIN_FFAST (12000000) /* ffast (12 MHz crystal) */
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/* HPLL0 configuration */
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#define BOARD_HPLL0_FINSEL CGU_HPFINSEL_FFAST /* Frequency input selection */
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#define BOARD_HPLL0_NDEC 131 /* PLL N-divider value */
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#define BOARD_HPLL0_MDEC 29784 /* PLL M-divider value */
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#define BOARD_HPLL0_PDEC 7 /* PLL P-divider value */
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#define BOARD_HPLL0_SELR 0 /* SELR bandwidth selection */
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#define BOARD_HPLL0_SELI 8 /* SELI bandwidth selection */
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#define BOARD_HPLL0_SELP 31 /* SELP bandwidth selection */
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#define BOARD_HPLL0_MODE 0 /* PLL mode */
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#define BOARD_HPLL0_FREQ 406425600 /* Frequency of the PLL in MHz */
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/* HPLL1 configuration */
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#define BOARD_HPLL1_FINSEL CGU_HPFINSEL_FFAST /* Frequency input selection */
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#define BOARD_HPLL1_NDEC 770 /* PLL N-divider value */
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#define BOARD_HPLL1_MDEC 8191 /* PLL M-divider value */
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#define BOARD_HPLL1_PDEC 98 /* PLL P-divider value */
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#define BOARD_HPLL1_SELR 0 /* SELR bandwidth selection */
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#define BOARD_HPLL1_SELI 16 /* SELI bandwidth selection */
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#define BOARD_HPLL1_SELP 8 /* SELP bandwidth selection */
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#define BOARD_HPLL1_MODE 0 /* PLL mode */
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#define BOARD_HPLL1_FREQ 180000000 /* Frequency of the PLL in MHz */
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/* The following 3 bitsets determine which clocks will be enabled at
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* initialization time.
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*/
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#define BOARD_CLKS_0_31 \
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(_RBIT(CLKID_APB0CLK,0)|_RBIT(CLKID_APB1CLK,0)|_RBIT(CLKID_APB2CLK,0)|\
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_RBIT(CLKID_APB3CLK,0)|_RBIT(CLKID_APB4CLK,0)|_RBIT(CLKID_AHB2INTCCLK,0)|\
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_RBIT(CLKID_AHB0CLK,0)|_RBIT(CLKID_ARM926CORECLK,0)|_RBIT(CLKID_ARM926BUSIFCLK,0)|\
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_RBIT(CLKID_ARM926RETIMECLK,0)|_RBIT(CLKID_ISRAM0CLK,0)|_RBIT(CLKID_ISRAM1CLK,0)|\
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_RBIT(CLKID_ISROMCLK,0)|_RBIT(CLKID_INTCCLK,0)|_RBIT(CLKID_AHB2APB0PCLK,0)|\
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_RBIT(CLKID_EVENTROUTERPCLK,0)|_RBIT(CLKID_CLOCKOUT,0))
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#define BOARD_CLKS_32_63 \
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(_RBIT(CLKID_IOCONFPCLK,32)|_RBIT(CLKID_CGUPCLK,32)|_RBIT(CLKID_SYSCREGPCLK,32)|\
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_RBIT(CLKID_OTPPCLK,32)|_RBIT(CLKID_AHB2APB1PCLK,32)|_RBIT(CLKID_AHB2APB2PCLK,32)|\
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_RBIT(CLKID_AHB2APB3PCLK,32)|_RBIT(CLKID_EDGEDETPCLK,32))
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#define BOARD_CLKS_64_92 \
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(0)
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/* LED definitions **********************************************************/
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#define LED_STARTED 0
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#define LED_HEAPALLOCATE 1
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#define LED_IRQSENABLED 2
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#define LED_STACKCREATED 3
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#define LED_INIRQ 4
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#define LED_SIGNAL 5
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#define LED_ASSERTION 6
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#define LED_PANIC 7
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/* Button definitions *******************************************************/
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#endif /* __BOARDS_ARM_LPC31XX_EA3131_INCLUDE_BOARD_H */
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