231 lines
8.6 KiB
C
231 lines
8.6 KiB
C
/************************************************************************************
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* configs/sama5df3x-ek/include/board_384mhz.h
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __CONFIGS_SAMA5D3X_EK_INCLUDE_BOARD_384MHZ_H
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#define __CONFIGS_SAMA5D3X_EK_INCLUDE_BOARD_384MHZ_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* Clocking *************************************************************************/
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/* After power-on reset, the SAMA5 device is running on a 12MHz internal RC. These
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* definitions will configure operational clocking.
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*
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* This is an alternative slower configuration that will produce a 48MHz USB clock
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* with the required accuracy. When used with OHCI, an additional requirement is
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* the PLLACK be a multiple of 48MHz. This setup results in a CPU clock of 384MHz.
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*
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* MAINOSC: Frequency = 12MHz (crystal)
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* PLLA: PLL Divider = 1, Multiplier = 64 to generate PLLACK = 768MHz
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* Master Clock (MCK): Source = PLLACK/2, Prescalar = 1, MDIV = 3 to generate
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* MCK = 128MHz
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* CPU clock = 384MHz
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*/
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/* Main oscillator register settings.
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*
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* The start up time should be should be:
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* Start Up Time = 8 * MOSCXTST / SLCK = 56 Slow Clock Cycles.
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*/
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#define BOARD_CKGR_MOR_MOSCXTST (62 << PMC_CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */
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/* PLLA configuration.
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*
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* Divider = 1
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* Multipler = 64
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*/
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#define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT)
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#define BOARD_CKGR_PLLAR_OUT (0)
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#define BOARD_CKGR_PLLAR_MUL (63 << PMC_CKGR_PLLAR_MUL_SHIFT)
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#define BOARD_CKGR_PLLAR_DIV PMC_CKGR_PLLAR_DIV_BYPASS
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/* PMC master clock register settings.
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*
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* Master/Processor Clock Source Selection = PLLA
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* Master/Processor Clock Prescaler = 1
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* PLLA Divider = 2
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* Master Clock Division (MDIV) = 3
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*
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* NOTE: Bit PLLADIV2 must always be set to 1 when MDIV is set to 3.
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*
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* Prescaler input = 768MHz / 2 = 384MHz
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* Prescaler output = 384MHz / 1 = 384MHz
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* Processor Clock (PCK) = 384MHz
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* Master clock (MCK) = 396MHz / 3 = 128MHz
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*/
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#define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLA
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#define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV1
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#define BOARD_PMC_MCKR_PLLADIV PMC_MCKR_PLLADIV2
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#define BOARD_PMC_MCKR_MDIV PMC_MCKR_MDIV_PCKDIV3
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#if defined(CONFIG_SAMA5_EHCI) || defined(CONFIG_SAMA5_OHCI) || \
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defined(CONFIG_SAMA5_UDPHS)
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/* For OHCI Full-speed operations, the user has to perform the following:
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*
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* 1) Enable UHP peripheral clock, bit (1 << AT91C_ID_UHPHS) in PMC_PCER
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* register.
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* 2) Select PLLACK as Input clock of OHCI part, USBS bit in PMC_USB
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* register.
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* 3) Program the OHCI clocks (UHP48M and UHP12M) with USBDIV field in
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* PMC_USB register. USBDIV value is calculated regarding the PLLACK
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* value and USB Full-speed accuracy.
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* 4) Enable the OHCI clocks, UHP bit in PMC_SCER register.
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*
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* "The USB Host controller requires 48 MHz and 12 MHz clocks for OHCI
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* full-speed operations. These clocks must be generated by a PLL with a
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* correct accuracy of <20> 0.25% thanks to USBDIV field.
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*
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* "Thus the USB Host peripheral receives three clocks from the Power
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* Management Controller (PMC): the Peripheral Clock (MCK domain), the
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* UHP48M and the UHP12M (built-in UHP48M divided by four) used by the
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* OHCI to interface with the bus USB signals (Recovered 12 MHz domain)
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* in Full-speed operations"
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*
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* USB Clock = PLLACK / (USBDIV + 1) = 48MHz
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* USBDIV = PLLACK / 48MHz - 1
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* = 15
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*
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* The maximum value of USBDIV is 15 corresponding to a divisor of 16.
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* REVISIT: However, using the divisor of (15+1) yields a frame rate
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* of 500 frames per second. A divisor of (7+1) gives the correct 1MS
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* frame rate. I cannot explain the factor of 2 difference.
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*/
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# undef BOARD_USE_UPLL /* Use PLLA as source clock */
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# define BOARD_OHCI_INPUT PMC_USB_USBS_PLLA /* Input is PLLACK */
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# if 1 /* REVISIT */
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# define BOARD_OHCI_DIVIDER (7) /* Divided by 8 */
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# else
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# define BOARD_OHCI_DIVIDER (15) /* Divided by 16 */
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# endif
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#endif
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/* ADC Configuration
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*
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* ADCClock = MCK / ((PRESCAL+1) * 2)
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*
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* Given:
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* MCK = 128MHz
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* ADCClock = 8MHz
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* Then:
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* PRESCAL = 7
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*/
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#define BOARD_ADC_PRESCAL (7)
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#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
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#define BOARD_TSD_TRACKTIM (2000) /* Min 1<>s at 8MHz */
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#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (unis nanoseconds) */
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/* Resulting frequencies */
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#define BOARD_MAINOSC_FREQUENCY (12000000) /* MAINOSC: 12MHz crystal on-board */
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#define BOARD_PLLA_FREQUENCY (768000000) /* PLLACK: 64 * 12Mhz / 1 */
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#define BOARD_PCK_FREQUENCY (384000000) /* CPU: PLLACK / 2 / 1 */
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#define BOARD_MCK_FREQUENCY (128000000) /* MCK: PLLACK / 2 / 1 / 3 */
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#define BOARD_ADCCLK_FREQUENCY (8000000) /* ADCCLK: MCK / ((7+1)*2) */
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/* HSMCI clocking
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*
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* Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK)
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* divided by (2*(CLKDIV) + CLOCKODD + 2).
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*
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* MCI_SPEED = MCK / (2*CLKDIV + CLOCKODD + 2)
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*
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* Where CLKDIV has a range of 0-255.
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*/
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/* MCK = 128MHz, CLKDIV = 159, MCI_SPEED = 128MHz / (2*159 + 0 + 2) = 400 KHz */
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#define HSMCI_INIT_CLKDIV (159 << HSMCI_MR_CLKDIV_SHIFT)
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/* MCK = 128MHz, CLKDIV = 2 w/CLOCKODD, MCI_SPEED = 128MHz /(2*2 + 1 + 2) = 18.3 MHz */
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#define HSMCI_MMCXFR_CLKDIV ((2 << HSMCI_MR_CLKDIV_SHIFT) | HSMCI_MR_CLKODD)
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/* MCK = 128MHz, CLKDIV = 2, MCI_SPEED = 128MHz /(2*2 + 0 + 2) = 21.3 MHz */
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#define HSMCI_SDXFR_CLKDIV (2 << HSMCI_MR_CLKDIV_SHIFT)
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#define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV
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/* FLASH wait states
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*
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* FWS Max frequency
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* 1.62V 1.8V
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* --- ----- ------
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* 0 24MHz 27MHz
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* 1 40MHz 47MHz
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* 2 72MHz 84MHz
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* 3 84MHz 96MHz
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*/
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#define BOARD_FWS 3
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/************************************************************************************
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* Public Data
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************************************************************************************/
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C" {
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#else
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#define EXTERN extern
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#endif
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/************************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* !__ASSEMBLY__ */
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#endif /* __CONFIGS_SAMA5D3X_EK_INCLUDE_BOARD_384MHZ_H */
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