783 lines
20 KiB
C
783 lines
20 KiB
C
/****************************************************************************
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* drivers/wireless/ieee80211/bcm43xxx/bcmf_core.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/compiler.h>
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#include <sys/types.h>
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#include <sys/stat.h>
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#include <assert.h>
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#include <debug.h>
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#include <errno.h>
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#include <fcntl.h>
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#include <inttypes.h>
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#include <string.h>
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#include <nuttx/arch.h>
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#include <nuttx/kmalloc.h>
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#include <nuttx/signal.h>
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#include "bcmf_core.h"
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#include "bcmf_interface.h"
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#include "bcmf_sdio_regs.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Agent registers (common for every core) */
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#define BCMA_IOCTL 0x0408 /* IO control */
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#define BCMA_IOST 0x0500 /* IO status */
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#define BCMA_RESET_CTL 0x0800 /* Reset control */
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#define BCMA_RESET_ST 0x0804
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#define BCMA_IOCTL_CLK 0x0001
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#define BCMA_IOCTL_FGC 0x0002
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#define BCMA_IOCTL_CORE_BITS 0x3FFC
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#define BCMA_IOCTL_PME_EN 0x4000
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#define BCMA_IOCTL_BIST_EN 0x8000
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/* ARM CR4 core specific control flag bits */
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#define ARMCR4_BCMA_IOCTL_CPUHALT 0x0020
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#define BCMA_IOST_CORE_BITS 0x0FFF
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#define BCMA_IOST_DMA64 0x1000
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#define BCMA_IOST_GATED_CLK 0x2000
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#define BCMA_IOST_BIST_ERROR 0x4000
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#define BCMA_IOST_BIST_DONE 0x8000
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#define BCMA_RESET_CTL_RESET 0x0001
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/* SOCSRAM core registers */
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#define SOCSRAM_BANKX_INDEX ((uint32_t) (0x18004000 + 0x10) )
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#define SOCSRAM_BANKX_PDA ((uint32_t) (0x18004000 + 0x44) )
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/* Define this to validate uploaded materials */
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/* #define DBG_VALIDATE_UPLOAD */
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/****************************************************************************
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* Private Types
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****************************************************************************/
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#ifdef DBG_VALIDATE_UPLOAD
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static uint8_t compare_buffer[BCMF_UPLOAD_TRANSFER_SIZE];
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#endif
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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static int bcmf_core_set_backplane_window(FAR bcmf_interface_dev_t *ibus,
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uint32_t address);
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static int bcmf_upload_binary(FAR bcmf_interface_dev_t *ibus,
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uint32_t address, uint8_t *buf,
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unsigned int len);
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static int bcmf_upload_nvram(FAR bcmf_interface_dev_t *ibus);
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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int bcmf_core_set_backplane_window(FAR bcmf_interface_dev_t *ibus,
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uint32_t address)
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{
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int ret;
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int i;
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address &= ~SBSDIO_SB_OFT_ADDR_MASK;
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for (i = 1; i < 4; i++)
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{
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uint8_t addr_part = (address >> (8*i)) & 0xff;
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uint8_t cur_addr_part = (ibus->backplane_current_addr >> (8*i)) & 0xff;
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if (addr_part != cur_addr_part)
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{
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/* Update current backplane base address */
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ret = bcmf_write_reg(ibus, 1, SBSDIO_FUNC1_SBADDRLOW + i - 1,
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addr_part);
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if (ret != OK)
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{
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return ret;
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}
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ibus->backplane_current_addr &= ~(0xff << (8*i));
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ibus->backplane_current_addr |= addr_part << (8*i);
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}
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}
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return OK;
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}
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int bcmf_upload_binary(FAR bcmf_interface_dev_t *ibus, uint32_t address,
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uint8_t *buf, unsigned int len)
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{
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unsigned int size;
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#ifdef DBG_VALIDATE_UPLOAD
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uint32_t validate_address = address;
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uint8_t *validate_buffer = buf;
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unsigned int validate_len = len;
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#endif
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while (len > 0)
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{
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/* Set the backplane window to include the start address */
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int ret = bcmf_core_set_backplane_window(ibus, address);
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if (ret != OK)
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{
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wlerr("Backplane setting failed at %08" PRIx32 "\n", address);
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return ret;
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}
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if (len > BCMF_UPLOAD_TRANSFER_SIZE)
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{
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size = BCMF_UPLOAD_TRANSFER_SIZE;
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}
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else
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{
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size = len;
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}
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/* Transfer firmware data */
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ret = bcmf_transfer_bytes(ibus, true, 1,
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address & SBSDIO_SB_OFT_ADDR_MASK, buf,
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size);
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if (ret != OK)
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{
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wlerr("transfer failed %d %" PRIx32 " %d\n", ret, address, size);
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return ret;
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}
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len -= size;
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address += size;
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buf += size;
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}
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#ifdef DBG_VALIDATE_UPLOAD
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wlwarn("Validating....\n");
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while (validate_len > 0)
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{
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/* Set the backplane window to include the start address */
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int ret = bcmf_core_set_backplane_window(ibus, validate_address);
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if (ret != OK)
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{
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wlerr("Backplane setting failed at %08x\n", validate_address);
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return ret;
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}
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if (validate_len > BCMF_UPLOAD_TRANSFER_SIZE)
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{
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size = BCMF_UPLOAD_TRANSFER_SIZE;
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}
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else
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{
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size = validate_len;
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}
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/* Transfer firmware data */
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ret = bcmf_transfer_bytes(ibus, false, 1,
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validate_address & SBSDIO_SB_OFT_ADDR_MASK,
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compare_buffer, size);
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if (ret != OK)
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{
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wlerr("validate transfer failed %d %x %d\n", ret, validate_address,
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size);
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return ret;
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}
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if (memcmp(validate_buffer, compare_buffer, size))
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{
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wlerr("Match failed at address base %08x\n", validate_address);
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return -EILSEQ;
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}
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validate_len -= size;
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validate_address += size;
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validate_buffer += size;
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}
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wlwarn("Validation passed\n");
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#endif
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return OK;
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}
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#ifdef CONFIG_IEEE80211_BROADCOM_FWFILES
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int bcmf_upload_file(FAR bcmf_interface_dev_t *ibus, uint32_t address,
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FAR const char *path)
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{
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struct file finfo;
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FAR uint8_t *buf;
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size_t total_read;
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ssize_t nread;
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int ret;
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/* Open the file in the detached state */
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ret = file_open(&finfo, path, O_RDONLY | O_CLOEXEC);
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if (ret < 0)
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{
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wlerr("ERROR: Failed to open the FILE MTD file %s: %d\n", path, ret);
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return ret;
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}
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/* Allocate an I/O buffer */
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buf = kmm_malloc(BCMF_UPLOAD_TRANSFER_SIZE);
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if (buf == NULL)
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{
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wlerr("ERROR: Failed allocate an I/O buffer\n");
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ret = -ENOMEM;
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goto errout_with_file;
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}
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/* Loop until the firmware has been loaded */
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do
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{
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/* Set the backplane window to include the start address */
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nread = file_read(&finfo, buf, BCMF_UPLOAD_TRANSFER_SIZE);
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if (nread < 0)
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{
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ret = (int)nread;
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wlerr("ERROR: Failed to read file: %d\n", ret);
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goto errout_with_buf;
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}
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if (nread == 0)
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{
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break;
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}
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wlinfo("Read %ld bytes\n", (long)nread);
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ret = bcmf_core_set_backplane_window(ibus, address);
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if (ret < 0)
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{
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wlerr("ERROR: bcmf_core_set_backplane_window() failed: %d\n", ret);
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goto errout_with_buf;
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}
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total_read = nread;
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/* Transfer firmware data */
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ret = bcmf_transfer_bytes(ibus, true, 1,
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address & SBSDIO_SB_OFT_ADDR_MASK, buf,
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total_read);
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if (ret < 0)
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{
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wlerr("ERROR: Transfer failed address=%lx total_read=%lu: %d\n",
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(unsigned long)address, (unsigned long)total_read, ret);
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goto errout_with_buf;
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}
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address += total_read;
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}
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while (nread == BCMF_UPLOAD_TRANSFER_SIZE);
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file_close(&finfo);
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kmm_free(buf);
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wlinfo("Upload complete\n");
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return OK;
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errout_with_buf:
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kmm_free(buf);
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errout_with_file:
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file_close(&finfo);
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return ret;
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}
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#endif
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int bcmf_upload_nvram(FAR bcmf_interface_dev_t *ibus)
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{
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FAR uint8_t *nvram_buf = ibus->chip->nvram_image;
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uint32_t nvram_sz = *ibus->chip->nvram_image_size;
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uint32_t token;
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int ret;
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#ifdef CONFIG_IEEE80211_BROADCOM_FWFILES
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FAR const char *nvfile = CONFIG_IEEE80211_BROADCOM_NVFILENAME;
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bool skipline = false;
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struct file finfo;
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struct stat stat;
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FAR uint8_t *buf;
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int i;
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if (strlen(nvfile) <= 0)
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{
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goto out;
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}
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ret = file_open(&finfo, nvfile, O_RDONLY | O_CLOEXEC);
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if (ret < 0)
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{
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goto out;
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}
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ret = file_fstat(&finfo, &stat);
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if (ret < 0 || stat.st_size <= 0)
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{
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goto out;
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}
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/* Round up the ram buffer size */
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stat.st_size = (stat.st_size + 63) & (~63);
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buf = kmm_malloc(stat.st_size);
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if (buf == NULL)
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{
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goto out;
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}
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/* Convert text pattern:
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* 1. Remove the comment line (Prefix with '#')
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* 2. Convert LF('\n') to NULL'\0'
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*/
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ret = file_read(&finfo, buf, stat.st_size);
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if (ret <= 0)
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{
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kmm_free(buf);
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goto out;
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}
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nvram_buf = buf;
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for (i = 0; i < ret; i++)
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{
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if (nvram_buf[i] == '\n')
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{
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if (buf != nvram_buf && *(buf - 1) != '\0')
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{
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*buf++ = '\0';
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}
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skipline = false;
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}
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else if (nvram_buf[i] == '#')
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{
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skipline = true;
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}
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else if (!skipline && (nvram_buf + i) != buf)
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{
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*buf++ = nvram_buf[i];
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}
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}
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nvram_sz = buf - nvram_buf;
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out:
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file_close(&finfo);
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#endif
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/* Round up the size of the image */
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nvram_sz = (nvram_sz + 63) & (~63);
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wlinfo("nvram size is %" PRId32 " bytes\n", nvram_sz);
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/* Write image */
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ret = bcmf_upload_binary(ibus,
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ibus->chip->ram_size - 4 - nvram_sz
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+ ibus->chip->ram_base,
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nvram_buf, nvram_sz);
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#ifdef CONFIG_IEEE80211_BROADCOM_FWFILES
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if (nvram_buf != ibus->chip->nvram_image)
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{
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kmm_free(nvram_buf);
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}
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#endif
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if (ret != OK)
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{
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return ret;
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}
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/* Generate length token */
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token = nvram_sz / 4;
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token = (~token << 16) | (token & 0x0000ffff);
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/* Write the length token to the last word */
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return bcmf_write_sbreg(ibus,
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ibus->chip->ram_size - 4 + ibus->chip->ram_base,
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(FAR uint8_t *)&token, 4);
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: bcmf_read_sbreg
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****************************************************************************/
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int bcmf_read_sbreg(FAR bcmf_interface_dev_t *ibus, uint32_t address,
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FAR uint8_t *reg, unsigned int len)
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{
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int ret = bcmf_core_set_backplane_window(ibus, address);
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if (ret != OK)
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{
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return ret;
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}
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address &= SBSDIO_SB_OFT_ADDR_MASK;
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/* Map to 32-bit access if len == 4 */
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if (len == 4)
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{
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address |= SBSDIO_SB_ACCESS_2_4B_FLAG;
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}
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return bcmf_transfer_bytes(ibus, false, 1, address, reg, len);
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}
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/****************************************************************************
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* Name: bcmf_write_sbreg
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****************************************************************************/
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int bcmf_write_sbreg(FAR bcmf_interface_dev_t *ibus, uint32_t address,
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FAR uint8_t *reg, unsigned int len)
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{
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int ret = bcmf_core_set_backplane_window(ibus, address);
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if (ret != OK)
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{
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return ret;
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}
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address &= SBSDIO_SB_OFT_ADDR_MASK;
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/* Map to 32-bit access if len == 4 */
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if (len == 4)
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{
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address |= SBSDIO_SB_ACCESS_2_4B_FLAG;
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}
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return bcmf_transfer_bytes(ibus, true, 1, address, reg, len);
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}
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/****************************************************************************
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* Name: bcmf_core_upload_firmware
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****************************************************************************/
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int bcmf_core_upload_firmware(FAR bcmf_interface_dev_t *ibus)
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{
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int ret;
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#if defined(CONFIG_IEEE80211_BROADCOM_BCM43455)
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uint32_t base;
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uint32_t value;
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#endif
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wlinfo("upload firmware\n");
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switch (ibus->cur_chip_id)
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{
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#if defined(CONFIG_IEEE80211_BROADCOM_BCM4301X) || \
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defined(CONFIG_IEEE80211_BROADCOM_BCM43362) || \
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defined(CONFIG_IEEE80211_BROADCOM_BCM43438) || \
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defined(CONFIG_IEEE80211_INFINEON_CYW43439)
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case SDIO_DEVICE_ID_BROADCOM_43012:
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case SDIO_DEVICE_ID_BROADCOM_43013:
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case SDIO_DEVICE_ID_BROADCOM_43362:
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case SDIO_DEVICE_ID_BROADCOM_43430:
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case SDIO_DEVICE_ID_INFINEON_CYW43439:
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/* Disable ARMCM3 core and reset SOCRAM core to set device in
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* firmware upload mode
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*/
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bcmf_core_disable(ibus, WLAN_ARMCM3_CORE_ID, 0, 0);
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bcmf_core_reset(ibus, SOCSRAM_CORE_ID, 0, 0, 0);
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#if defined(CONFIG_IEEE80211_BROADCOM_BCM43438) \
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|| defined(CONFIG_IEEE80211_INFINEON_CYW43439)
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if (ibus->cur_chip_id == SDIO_DEVICE_ID_BROADCOM_43430)
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{
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/* Disable remap for SRAM_3. Only for 4343x */
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bcmf_write_sbregw(ibus, SOCSRAM_BANKX_INDEX, 0x3);
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bcmf_write_sbregw(ibus, SOCSRAM_BANKX_PDA, 0);
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}
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#endif
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break;
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#endif
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#if defined(CONFIG_IEEE80211_BROADCOM_BCM43455)
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case SDIO_DEVICE_ID_BROADCOM_43455:
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/* Clear all IOCTL bits except HALT bit */
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base = ibus->chip->core_base[WLAN_ARMCR4_CORE_ID];
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bcmf_read_sbregw(ibus, base + BCMA_IOCTL, &value);
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value &= ARMCR4_BCMA_IOCTL_CPUHALT;
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bcmf_core_reset(ibus,
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WLAN_ARMCR4_CORE_ID,
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value,
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ARMCR4_BCMA_IOCTL_CPUHALT,
|
|
ARMCR4_BCMA_IOCTL_CPUHALT);
|
|
break;
|
|
#endif
|
|
|
|
default:
|
|
DEBUGPANIC();
|
|
}
|
|
|
|
nxsig_usleep(50 * 1000);
|
|
|
|
/* Flash chip firmware */
|
|
|
|
#ifdef CONFIG_IEEE80211_BROADCOM_FWFILES
|
|
ret = bcmf_upload_file(ibus,
|
|
ibus->chip->ram_base,
|
|
CONFIG_IEEE80211_BROADCOM_FWFILENAME);
|
|
#else
|
|
wlinfo("firmware size is %d bytes\n", *ibus->chip->firmware_image_size);
|
|
|
|
ret = bcmf_upload_binary(ibus,
|
|
ibus->chip->ram_base,
|
|
ibus->chip->firmware_image,
|
|
*ibus->chip->firmware_image_size);
|
|
#endif
|
|
|
|
if (ret < 0)
|
|
{
|
|
wlerr("ERROR: Failed to upload firmware\n");
|
|
return ret;
|
|
}
|
|
|
|
/* Flash NVRAM configuration file */
|
|
|
|
wlinfo("upload nvram configuration\n");
|
|
ret = bcmf_upload_nvram(ibus);
|
|
if (ret < 0)
|
|
{
|
|
wlerr("ERROR: Failed to upload NVRAM\n");
|
|
return ret;
|
|
}
|
|
|
|
/* Firmware upload done, restart ARM CM3/CR4 core */
|
|
|
|
switch (ibus->cur_chip_id)
|
|
{
|
|
#if defined(CONFIG_IEEE80211_BROADCOM_BCM4301X) || \
|
|
defined(CONFIG_IEEE80211_BROADCOM_BCM43362) || \
|
|
defined(CONFIG_IEEE80211_BROADCOM_BCM43438) || \
|
|
defined(CONFIG_IEEE80211_INFINEON_CYW43439)
|
|
|
|
case SDIO_DEVICE_ID_BROADCOM_43012:
|
|
case SDIO_DEVICE_ID_BROADCOM_43013:
|
|
case SDIO_DEVICE_ID_BROADCOM_43362:
|
|
case SDIO_DEVICE_ID_BROADCOM_43430:
|
|
case SDIO_DEVICE_ID_INFINEON_CYW43439:
|
|
nxsig_usleep(10 * 1000);
|
|
bcmf_core_reset(ibus, WLAN_ARMCM3_CORE_ID, 0, 0, 0);
|
|
|
|
/* Check ARMCM3 core is running */
|
|
|
|
nxsig_usleep(10 * 1000);
|
|
if (!bcmf_core_isup(ibus, WLAN_ARMCM3_CORE_ID))
|
|
{
|
|
wlerr("Cannot start ARMCM3 core\n");
|
|
return -ETIMEDOUT;
|
|
}
|
|
break;
|
|
#endif
|
|
|
|
#if defined(CONFIG_IEEE80211_BROADCOM_BCM43455)
|
|
|
|
case SDIO_DEVICE_ID_BROADCOM_43455:
|
|
|
|
/* Clear all interrupts */
|
|
|
|
bcmf_write_sbregw(
|
|
ibus,
|
|
CORE_BUS_REG(ibus->chip->core_base[SDIOD_CORE_ID], intstatus),
|
|
0xffffffff);
|
|
|
|
/* Write reset vector to address 0 */
|
|
|
|
ret = bcmf_upload_binary(ibus,
|
|
0,
|
|
ibus->chip->firmware_image,
|
|
4);
|
|
if (ret < 0)
|
|
{
|
|
return ret;
|
|
}
|
|
|
|
bcmf_core_reset(ibus,
|
|
WLAN_ARMCR4_CORE_ID,
|
|
ARMCR4_BCMA_IOCTL_CPUHALT,
|
|
0,
|
|
0);
|
|
|
|
/* Check ARMCR4 core is running */
|
|
|
|
nxsig_usleep(10 * 1000);
|
|
if (!bcmf_core_isup(ibus, WLAN_ARMCR4_CORE_ID))
|
|
{
|
|
wlerr("Cannot start ARMCR4 core\n");
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
break;
|
|
#endif
|
|
|
|
default:
|
|
DEBUGPANIC();
|
|
}
|
|
|
|
return OK;
|
|
}
|
|
|
|
bool bcmf_core_isup(FAR bcmf_interface_dev_t *ibus, unsigned int core)
|
|
{
|
|
uint32_t value = 0;
|
|
uint32_t base;
|
|
|
|
if (core >= MAX_CORE_ID)
|
|
{
|
|
wlerr("Invalid core id %d\n", core);
|
|
return false;
|
|
}
|
|
|
|
base = ibus->chip->core_base[core];
|
|
|
|
bcmf_read_sbregw(ibus, base + BCMA_IOCTL, &value);
|
|
|
|
if ((value & (BCMA_IOCTL_FGC | BCMA_IOCTL_CLK)) != BCMA_IOCTL_CLK)
|
|
{
|
|
return false;
|
|
}
|
|
|
|
bcmf_read_sbregw(ibus, base + BCMA_RESET_CTL, &value);
|
|
|
|
return (value & BCMA_RESET_CTL_RESET) == 0;
|
|
}
|
|
|
|
void bcmf_core_disable(FAR bcmf_interface_dev_t *ibus,
|
|
unsigned int core,
|
|
uint32_t prereset,
|
|
uint32_t reset)
|
|
{
|
|
uint32_t value;
|
|
|
|
if (core >= MAX_CORE_ID)
|
|
{
|
|
wlerr("Invalid core id %d\n", core);
|
|
return;
|
|
}
|
|
|
|
uint32_t base = ibus->chip->core_base[core];
|
|
|
|
/* Check if core is already in reset state.
|
|
* If core is already in reset state, skip reset.
|
|
*/
|
|
|
|
bcmf_read_sbregw(ibus, base + BCMA_RESET_CTL, &value);
|
|
|
|
if ((value & BCMA_RESET_CTL_RESET) == 0)
|
|
{
|
|
/* Core is not in reset state */
|
|
|
|
/* Ensure no backplane operation is pending */
|
|
|
|
nxsig_usleep(10 * 1000);
|
|
|
|
bcmf_write_sbregw(ibus,
|
|
base + BCMA_IOCTL,
|
|
prereset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK);
|
|
bcmf_read_sbregw(ibus, base + BCMA_IOCTL, &value);
|
|
|
|
/* Set core in reset state */
|
|
|
|
bcmf_write_sbregw(ibus, base + BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
|
|
up_udelay(1);
|
|
}
|
|
|
|
bcmf_write_sbregw(ibus,
|
|
base + BCMA_IOCTL,
|
|
reset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK);
|
|
bcmf_read_sbregw(ibus, base + BCMA_IOCTL, &value);
|
|
up_udelay(10);
|
|
}
|
|
|
|
void bcmf_core_reset(FAR bcmf_interface_dev_t *ibus,
|
|
unsigned int core,
|
|
uint32_t prereset,
|
|
uint32_t reset,
|
|
uint32_t postreset)
|
|
{
|
|
uint32_t value;
|
|
uint32_t base;
|
|
|
|
if (core >= MAX_CORE_ID)
|
|
{
|
|
wlerr("Invalid core id %d\n", core);
|
|
return;
|
|
}
|
|
|
|
base = ibus->chip->core_base[core];
|
|
|
|
/* Put core in reset state */
|
|
|
|
bcmf_core_disable(ibus, core, prereset, reset);
|
|
|
|
/* Run initialization sequence */
|
|
|
|
bcmf_write_sbregw(ibus, base + BCMA_RESET_CTL, 0);
|
|
bcmf_read_sbregw(ibus, base + BCMA_RESET_CTL, &value);
|
|
|
|
up_udelay(1);
|
|
|
|
bcmf_write_sbregw(ibus, base + BCMA_IOCTL, postreset | BCMA_IOCTL_CLK);
|
|
bcmf_read_sbregw(ibus, base + BCMA_IOCTL, &value);
|
|
|
|
up_udelay(1);
|
|
}
|