b984752aec
* arch: x86_64: Pour-in the x86_64 code from cRTOS repository, excluding modifications of NuttX kernel, jailhouse support and linux compatibility layer * arch: x86_64: Refactor x86_64 loading procedure for better comprehension and included support for multiboot2 * arch: x86_64: Locate the kernel at 4GB~ and modify the page table initializing procedure accordingly * arch: x86_64: Implemented kconfig option for various x86_64 capabilities, dynamic probe and check capability on lowsetup before enabling * arch: x86_64: inte64_check_capability: Use Marco to prettify the capability checking procedure * arch: x86_64: intel64_timerisr.c: Refactor with new frequency calibrating method * arch: x86_64: Fix C alias of page table and GDT/IST * arch: x86_64: Reload GTDR with GDT in high address in up_lowsetup * arch: x86_64: Consolidate MSR definition in arch/arch.h * arch: x86_64: Edit the way of handling GDT/IST in C into structures * arch: x86_64: Correct the starting point of isr/irq stack * arch: x86_64: Update up_initialize.c with the new initializing procedure * arch: x86_64: up_map_region now take flags instead of assuming WR/PRESENT * arch: x86_64: Overhual of interrupt initialization procedure * arch: x86_64: Properly configure the heap to be memory as [_ebss, end of memory] * arch: x86_64: Try to probe the TSC frequency, fall-back to user specified frequency on failure * arch: x86_64: Remove debug printing during restore_aux, causing infinite CTX bug * arch: x86_64: for X86 16500 serial interrupt to work, OUT2 of MCR must be 1. Make it stuck at 1 after boot * arch: x86_64: Correctly apply license header, comment and format code * arch: x86_64: properly send a SIGFPE on floating point error * arch: x86_64: Remove unused variable in up_restore_auxstate * arch: x86_64: properly trash the processor with an infinite loop * arch: x86_64: Fix typo in ISR handler causing ISR not handled * arch: x86_64: Fix possibile race conditions with scheduler debug option on in signal handling path * arch: x86_64: Fix typo in MSR_X2APIC_LVTT_TSC_DEADLINE * arch: x86_64: Migrate tickless implementation to the new MSR naming and frequency calibration method * board: x86_64: qemu: Add guard to exclude up_netinitialize when compiling without net support * arch: x86_64: update defconfigs * arch: x86_64: rename qemu as qemu-intel64 * arch: x86_64: update Board readme
68 lines
1.2 KiB
Plaintext
68 lines
1.2 KiB
Plaintext
#
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# For a description of the syntax of this configuration file,
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# see the file kconfig-language.txt in the NuttX tools repository.
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#
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if ARCH_X86_64
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comment "x86_64 Configuration Options"
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config ARCH
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string
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default "x86_64"
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choice
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prompt "x86_64 arch selection"
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default ARCH_INTEL64
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config ARCH_INTEL64
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bool "Intel x86_64"
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select ARCH_HAVE_MPU
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select ARCH_USE_MPU
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select ARCH_HAVE_TICKLESS
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select ARCH_HAVE_STACKCHECK
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select ARCH_HAVE_RNG
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---help---
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Intel x86_64 architecture
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endchoice
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choice
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prompt "x86_64 system selection"
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default ARCH_BOARD_QEMU
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config ARCH_BOARD_QEMU
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bool "Qemu envrionment"
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---help---
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Targeting virtualized qemu environment
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endchoice
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source arch/x86_64/src/common/Kconfig
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if ARCH_INTEL64
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source arch/x86_64/src/intel64/Kconfig
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config ARCH_CHIP
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string
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default "intel64"
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endif # ARCH_INTEL64
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if ARCH_BOARD_QEMU
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source arch/x86_64/src/qemu/Kconfig
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config ARCH_BOARD
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string
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default "qemu-intel64"
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endif # ARCH_CHIP_QEMU
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config ARCH_EXCLUDE_MULTIBOOT
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bool "Don't append multiboot2 header"
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default n
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---help---
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Some platforms, e.g. jailhouse, do not like to have a multiboot header
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endif # ARCH_X86_64
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