106 lines
4.2 KiB
Plaintext
106 lines
4.2 KiB
Plaintext
/****************************************************************************
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* boards/xtensa/esp32/common/scripts/protected_memory.ld
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* ESP32 Linker Script Memory Layout for Protected Mode
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*
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* This file describes the memory layout (memory blocks) as virtual
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* memory addresses.
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*
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* kernel-space.ld and user-space.ld contain output sections to link compiler
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* output into these memory blocks for the Kernel and User images,
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* respectively.
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*
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****************************************************************************/
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#include <nuttx/config.h>
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#include "esp32_aliases.ld"
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MEMORY
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{
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metadata (RX) : org = 0x0, len = 0x18
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ROM (RX) : org = ORIGIN(metadata) + LENGTH(metadata),
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len = 0x100000 - ORIGIN(ROM)
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/* Below values assume the flash cache is on, and have the blocks this
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* uses subtracted from the length of the various regions. The 'data access
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* port' dram/drom regions map to the same iram/irom regions but are
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* connected to the data port of the CPU and e.g. allow bytewise access.
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*/
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/* Physically located in SRAM0 */
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KIRAM_0 (RWX) : org = 0x40080000, len = 0x2000
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UIRAM (RWX) : org = 0x40082000, len = 0xe000
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KIRAM_1 (RWX) : org = 0x40090000, len = 0x10000
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/* Flash mapped instruction data. */
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/* The 0x20 offset for the KIROM region is a convenience for the Kernel
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* binary image generation in Espressif Application Image format.
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* Flash cache has 64KB pages. The .bin file which is flashed to the chip
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* has a 0x18 byte file header, and each segment has a 0x08 byte segment
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* header. Setting this offset makes it simple to meet the flash cache MMU's
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* constraint that (paddr % 64KB == vaddr % 64KB).
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*/
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KIROM (RX) : org = 0x400d0020, len = 0x330000 - 0x20
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UIROM (RX) : org = 0x40400000, len = 0x400000
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/* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
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* Enabling Bluetooth & Trace Memory features in menuconfig will decrease
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* the amount of RAM available to the NuttX Kernel.
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*/
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#ifdef CONFIG_ESP32_USER_DATA_EXTMEM
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/* Physically located in External RAM */
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UDRAM (RW) : org = 0x3f800000, len = 0x400000
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/* Physically located in SRAM2 */
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KDRAM_0 (RW) : org = 0x3ffb0000 + CONFIG_ESP32_BT_RESERVE_DRAM,
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len = 0x30000 - CONFIG_ESP32_BT_RESERVE_DRAM
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/* Physically located in SRAM1 */
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KDRAM_1 (RW) : org = 0x3ffe0000, len = 0x20000
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#else
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/* Physically located in SRAM2 */
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KDRAM_0 (RW) : org = 0x3ffb0000 + CONFIG_ESP32_BT_RESERVE_DRAM,
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len = 0x18000 - CONFIG_ESP32_BT_RESERVE_DRAM
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UDRAM (RW) : org = 0x3ffc8000, len = 0x18000
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/* Physically located in SRAM1 */
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KDRAM_1 (RW) : org = 0x3ffe0000, len = 0x20000
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#endif
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/* Flash mapped constant data */
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/* See KIROM region documentation above for the meaning of the 0x20 offset.
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*
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* The 0x18 offset for the UDROM region is a convenience for the User
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* binary image generation following a custom image format, which defines
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* a "metadata" output section containing some information that the Kernel
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* needs for properly configuring the External Flash MMU when loading the
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* User application image.
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*/
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KDROM (R) : org = 0x3f400020, len = 0x80000 - 0x20
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UDROM (R) : org = 0x3f480018, len = 0x80000 - ORIGIN(ROM)
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}
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