Huang Qi 676d35f007 risc-v: Make exception_common 8 byte align ... Some SoC like bl602 require the exception entry 8 byte align, it should be safe for other chips so we can apply it globally. Signed-off-by: Huang Qi <huangqi3@xiaomi.com>		2022-01-17 11:44:50 +08:00
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include	arch/risc-v/qemu-rv: Support both rv32/rv64 core	2022-01-15 11:42:01 +08:00
src	risc-v: Make exception_common 8 byte align	2022-01-17 11:44:50 +08:00
Kconfig	risc-v: Remove ARCH_RV_ISA_[F|D] use ARCH_HAVE_FPU instead	2022-01-15 11:42:01 +08:00