132 lines
4.8 KiB
C
132 lines
4.8 KiB
C
/****************************************************************************
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* arch/arm/src/stm32f7/stm32_lse.c
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*
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* Copyright (C) 2017 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* David Sidrane <david_s5@nscdg.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "up_arch.h"
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#include "stm32_rcc.h"
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#include "stm32_pwr.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#ifdef CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY
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# if CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \
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CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY > 3
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# error "Invalid LSE drive capability setting"
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#endif
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#endif
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#ifdef CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY
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# if CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \
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CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3
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# error "Invalid LSE drive capability setting"
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#endif
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_rcc_enablelse
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*
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* Description:
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* Enable the External Low-Speed (LSE) oscillator.
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*
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****************************************************************************/
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void stm32_rcc_enablelse(void)
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{
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uint32_t regval;
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/* Check if the External Low-Speed (LSE) oscillator is already running. */
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regval = getreg32(STM32_RCC_BDCR);
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if ((regval & (RCC_BDCR_LSEON | RCC_BDCR_LSERDY)) !=
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(RCC_BDCR_LSEON | RCC_BDCR_LSERDY))
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{
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/* The LSE is in the RTC domain and write access is denied to this
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* domain after reset, you have to enable write access using DBP bit
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* in the PWR CR register before to configuring the LSE.
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*/
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stm32_pwr_enablebkp(true);
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/* Enable the External Low-Speed (LSE) oscillator by setting the
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* LSEON bit the RCC BDCR register.
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*/
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regval |= RCC_BDCR_LSEON;
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#ifdef CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY
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/* Set start-up drive capability for LSE oscillator. */
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regval &= ~RCC_BDCR_LSEDRV_MASK;
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regval |= CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY <<
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RCC_BDCR_LSEDRV_SHIFT;
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#endif
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putreg32(regval, STM32_RCC_BDCR);
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/* Wait for the LSE clock to be ready */
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while (((regval = getreg32(STM32_RCC_BDCR)) & RCC_BDCR_LSERDY) == 0);
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#if defined(CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \
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CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY != \
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CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY
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/* Set running drive capability for LSE oscillator. */
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regval &= ~RCC_BDCR_LSEDRV_MASK;
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regval |= CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY <<
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RCC_BDCR_LSEDRV_SHIFT;
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putreg32(regval, STM32_RCC_BDCR);
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#endif
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/* Disable backup domain access if it was disabled on entry */
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stm32_pwr_enablebkp(false);
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}
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}
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