Gregory Nutt 371639637f SAMA5: Correct the PLL 48MHz divisor. It was off by a factor of two... no idea why		2013-08-14 19:38:48 -06:00
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board_384mhz.h	SAMA5: Correct the PLL 48MHz divisor. It was off by a factor of two... no idea why	2013-08-14 19:38:48 -06:00
board_396mhz.h	SAMA5: Correct the PLL 48MHz divisor. It was off by a factor of two... no idea why	2013-08-14 19:38:48 -06:00
board_memorymap.h	A few more SAMA5D3 files	2013-07-19 17:45:28 -06:00
board.h	SAMA5: Alternatie clock configuration that yields a perfect 48MHz full speed USB clock and a CPU clock of 384MHz	2013-08-14 15:16:04 -06:00