439 lines
17 KiB
C
439 lines
17 KiB
C
/************************************************************************************
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* configs/stm32f746g-disco/include/board.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __CONFIG_STM32F746G_DISCO_INCLUDE_BOARD_H
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#define __CONFIG_STM32F746G_DISCO_INCLUDE_BOARD_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Clocking *************************************************************************/
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/* The STM32F7 Discovery board provides the following clock sources:
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*
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* X1: 24 MHz oscillator for USB OTG HS PHY and camera module (daughter board)
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* X2: 25 MHz oscillator for STM32F746NGH6 microcontroller and Ethernet PHY.
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* X3: 32.768 KHz crystal for STM32F746NGH6 embedded RTC
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*
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* So we have these clock source available within the STM32
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*
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* HSI: 16 MHz RC factory-trimmed
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* LSI: 32 KHz RC
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* HSE: On-board crystal frequency is 25MHz
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* LSE: 32.768 kHz
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*/
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#define STM32_BOARD_XTAL 25000000ul
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#define STM32_HSI_FREQUENCY 16000000ul
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#define STM32_LSI_FREQUENCY 32000
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_LSE_FREQUENCY 32768
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/* Main PLL Configuration.
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*
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* PLL source is HSE = 25,000,000
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*
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* PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
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* Subject to:
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*
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* 2 <= PLLM <= 63
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* 192 <= PLLN <= 432
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* 192 MHz <= PLL_VCO <= 432MHz
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*
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* SYSCLK = PLL_VCO / PLLP
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* Subject to
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*
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* PLLP = {2, 4, 6, 8}
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* SYSCLK <= 216 MHz
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*
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* USB OTG FS, SDMMC and RNG Clock = PLL_VCO / PLLQ
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* Subject to
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* The USB OTG FS requires a 48 MHz clock to work correctly. The SDMMC
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* and the random number generator need a frequency lower than or equal
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* to 48 MHz to work correctly.
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*
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* 2 <= PLLQ <= 15
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*/
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#if defined(CONFIG_STM32F7_OTGFS)
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/* Highest SYSCLK with USB OTG FS clock = 48 MHz
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*
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* PLL_VCO = (25,000,000 / 25) * 384 = 384 MHz
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* SYSCLK = 384 MHz / 2 = 192 MHz
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* USB OTG FS, SDMMC and RNG Clock = 384 MHz / 8 = 48MHz
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*/
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25)
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(384)
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
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#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8)
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#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 25) * 384)
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#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2)
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#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 8)
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#elif defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_RNG)
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/* Highest SYSCLK with USB OTG FS clock <= 48MHz
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*
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* PLL_VCO = (25,000,000 / 25) * 432 = 432 MHz
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* SYSCLK = 432 MHz / 2 = 216 MHz
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* USB OTG FS, SDMMC and RNG Clock = 432 MHz / 10 = 43.2 MHz
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*/
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25)
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(432)
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
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#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(10)
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#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 25) * 432)
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#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2)
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#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 10)
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#else
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/* Highest SYSCLK
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*
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* PLL_VCO = (25,000,000 / 25) * 432 = 432 MHz
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* SYSCLK = 432 MHz / 2 = 216 MHz
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*/
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25)
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(432)
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
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#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(10)
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#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 25) * 432)
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#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2)
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#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 10)
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#endif
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/* Configure factors for PLLSAI clock */
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#define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(BOARD_LTDC_PLLSAIN)
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#define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(2)
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#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(2)
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#define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(BOARD_LTDC_PLLSAIR)
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/* Configure Dedicated Clock Configuration Register */
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#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(1)
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#define STM32_RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ(1)
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#define STM32_RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR(1)
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#define STM32_RCC_DCKCFGR1_SAI1SRC RCC_DCKCFGR1_SAI1SEL(0)
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#define STM32_RCC_DCKCFGR1_SAI2SRC RCC_DCKCFGR1_SAI2SEL(0)
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#define STM32_RCC_DCKCFGR1_TIMPRESRC 0
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#define STM32_RCC_DCKCFGR1_DFSDM1SRC 0
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#define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0
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/* Configure factors for PLLI2S clock */
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#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2)
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/* Configure Dedicated Clock Configuration Register 2 */
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#define STM32_RCC_DCKCFGR2_USART1SRC RCC_DCKCFGR2_USART1SEL_APB
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#define STM32_RCC_DCKCFGR2_USART2SRC RCC_DCKCFGR2_USART2SEL_APB
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#define STM32_RCC_DCKCFGR2_UART4SRC RCC_DCKCFGR2_UART4SEL_APB
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#define STM32_RCC_DCKCFGR2_UART5SRC RCC_DCKCFGR2_UART5SEL_APB
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#define STM32_RCC_DCKCFGR2_USART6SRC RCC_DCKCFGR2_USART6SEL_APB
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#define STM32_RCC_DCKCFGR2_UART7SRC RCC_DCKCFGR2_UART7SEL_APB
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#define STM32_RCC_DCKCFGR2_UART8SRC RCC_DCKCFGR2_UART8SEL_APB
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#define STM32_RCC_DCKCFGR2_I2C1SRC RCC_DCKCFGR2_I2C1SEL_HSI
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#define STM32_RCC_DCKCFGR2_I2C2SRC RCC_DCKCFGR2_I2C2SEL_HSI
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#define STM32_RCC_DCKCFGR2_I2C3SRC RCC_DCKCFGR2_I2C3SEL_HSI
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#define STM32_RCC_DCKCFGR2_I2C4SRC RCC_DCKCFGR2_I2C4SEL_HSI
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#define STM32_RCC_DCKCFGR2_LPTIM1SRC RCC_DCKCFGR2_LPTIM1SEL_APB
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#define STM32_RCC_DCKCFGR2_CECSRC RCC_DCKCFGR2_CECSEL_HSI
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#define STM32_RCC_DCKCFGR2_CK48MSRC RCC_DCKCFGR2_CK48MSEL_PLLSAI
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#define STM32_RCC_DCKCFGR2_SDMMCSRC RCC_DCKCFGR2_SDMMCSEL_48MHZ
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#define STM32_RCC_DCKCFGR2_SDMMC2SRC RCC_DCKCFGR2_SDMMC2SEL_48MHZ
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/* Several prescalers allow the configuration of the two AHB buses, the
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* high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum
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* frequency of the two AHB buses is 216 MHz while the maximum frequency of
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* the high-speed APB domains is 108 MHz. The maximum allowed frequency of
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* the low-speed APB domain is 54 MHz.
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*/
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/* AHB clock (HCLK) is SYSCLK (216 MHz) */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
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/* APB1 clock (PCLK1) is HCLK/4 (54 MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
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/* Timers driven from APB1 will be twice PCLK1 */
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
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/* APB2 clock (PCLK2) is HCLK/2 (108MHz) */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* Timers driven from APB2 will be twice PCLK2 */
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#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY)
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/* FLASH wait states
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*
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* --------- ---------- -----------
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* VDD MAX SYSCLK WAIT STATES
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* --------- ---------- -----------
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* 1.7-2.1 V 180 MHz 8
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* 2.1-2.4 V 216 MHz 9
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* 2.4-2.7 V 216 MHz 8
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* 2.7-3.6 V 216 MHz 7
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* --------- ---------- -----------
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*/
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#define BOARD_FLASH_WAITSTATES 7
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/* LED definitions ******************************************************************/
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/* The STM32F746G-DISCO board has numerous LEDs but only one, LD1 located near the
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* reset button, that can be controlled by software (LD2 is a power indicator, LD3-6
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* indicate USB status, LD7 is controlled by the ST-Link).
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*
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* LD1 is controlled by PI1 which is also the SPI2_SCK at the Arduino interface.
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* One end of LD1 is grounded so a high output on PI1 will illuminate the LED.
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*
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* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any way.
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* The following definitions are used to access individual LEDs.
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_LED1 0
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#define BOARD_NLEDS 1
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#define BOARD_LD1 BOARD_LED1
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/* LED bits for use with board_userled_all() */
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#define BOARD_LED1_BIT (1 << BOARD_LED1)
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/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in
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* include/board.h and src/stm32_leds.c. The LEDs are used to encode OS-related
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* events as follows:
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*
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* SYMBOL Meaning LD1
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* ------------------- ----------------------- ------
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* LED_STARTED NuttX has been started OFF
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* LED_HEAPALLOCATE Heap has been allocated OFF
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* LED_IRQSENABLED Interrupts enabled OFF
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* LED_STACKCREATED Idle stack created ON
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* LED_INIRQ In an interrupt N/C
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* LED_SIGNAL In a signal handler N/C
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* LED_ASSERTION An assertion failed N/C
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* LED_PANIC The system has crashed FLASH
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*
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* Thus is LD1 is statically on, NuttX has successfully booted and is,
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* apparently, running normally. If LD1 is flashing at approximately
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* 2Hz, then a fatal error has been detected and the system has halted.
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*/
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#define LED_STARTED 0 /* LD1=OFF */
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#define LED_HEAPALLOCATE 0 /* LD1=OFF */
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#define LED_IRQSENABLED 0 /* LD1=OFF */
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#define LED_STACKCREATED 1 /* LD1=ON */
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#define LED_INIRQ 2 /* LD1=no change */
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#define LED_SIGNAL 2 /* LD1=no change */
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#define LED_ASSERTION 2 /* LD1=no change */
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#define LED_PANIC 3 /* LD1=flashing */
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/* Button definitions ***************************************************************/
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/* The STM32F7 Discovery supports one button: Pushbutton B1, labelled "User", is
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* connected to GPIO PI11. A high value will be sensed when the button is depressed.
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*/
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#define BUTTON_USER 0
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#define NUM_BUTTONS 1
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#define BUTTON_USER_BIT (1 << BUTTON_USER)
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/* Alternate function pin selections ************************************************/
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/* USART6:
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*
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* These configurations assume that you are using a standard Arduio RS-232 shield
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* with the serial interface with RX on pin D0 and TX on pin D1:
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*
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* -------- ---------------
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* STM32F7
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* ARDUIONO FUNCTION GPIO
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* -- ----- --------- -----
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* DO RX USART6_RX PC7
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* D1 TX USART6_TX PC6
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* -- ----- --------- -----
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*/
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#define GPIO_USART6_RX GPIO_USART6_RX_1
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#define GPIO_USART6_TX GPIO_USART6_TX_1
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/* USART1:
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*
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* USART1 is connected to the "Virtual Com Port" lines of the ST-LINK controller.
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*
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* -------- ---------------
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* STM32F7
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* SIGNAME FUNCTION GPIO
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* -- ----- --------- -----
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* VCP_RX USART1_RX PB7
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* VCP_TX USART1_TX PA9
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* -- ----- --------- -----
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*/
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#define GPIO_USART1_RX GPIO_USART1_RX_2
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#define GPIO_USART1_TX GPIO_USART1_TX_1
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/* The STM32 F7 connects to a SMSC LAN8742A PHY using these pins:
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*
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* STM32 F7 BOARD LAN8742A
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* GPIO SIGNAL PIN NAME
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* -------- ------------ -------------
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* PG11 RMII_TX_EN TXEN
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* PG13 RMII_TXD0 TXD0
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* PG14 RMII_TXD1 TXD1
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* PC4 RMII_RXD0 RXD0/MODE0
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* PC5 RMII_RXD1 RXD1/MODE1
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* PG2 RMII_RXER RXER/PHYAD0 -- Not used
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* PA7 RMII_CRS_DV CRS_DV/MODE2
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* PC1 RMII_MDC MDC
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* PA2 RMII_MDIO MDIO
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* N/A NRST nRST
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* PA1 RMII_REF_CLK nINT/REFCLK0
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* N/A OSC_25M XTAL1/CLKIN
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*
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* The PHY address is either 0 or 1, depending on the state of PG2 on reset.
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* PG2 is not controlled but appears to result in a PHY address of 0.
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*/
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#define GPIO_ETH_RMII_TX_EN GPIO_ETH_RMII_TX_EN_2
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#define GPIO_ETH_RMII_TXD0 GPIO_ETH_RMII_TXD0_2
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#define GPIO_ETH_RMII_TXD1 GPIO_ETH_RMII_TXD1_2
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/* LCD definitions ******************************************************************/
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#define BOARD_LTDC_WIDTH 480
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#define BOARD_LTDC_HEIGHT 272
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#define BOARD_LTDC_OUTPUT_BPP 24
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#define BOARD_LTDC_HFP 32
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#define BOARD_LTDC_HBP 13
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#define BOARD_LTDC_VFP 2
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#define BOARD_LTDC_VBP 2
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#define BOARD_LTDC_HSYNC 41
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#define BOARD_LTDC_VSYNC 10
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#define BOARD_LTDC_PLLSAIN 192
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#define BOARD_LTDC_PLLSAIR 5
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/* Pixel Clock Polarity */
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#define BOARD_LTDC_GCR_PCPOL 0 /* !LTDC_GCR_PCPOL */
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/* Data Enable Polarity */
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#define BOARD_LTDC_GCR_DEPOL 0 /* !LTDC_GCR_DEPOL */
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/* Vertical Sync Polarity */
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#define BOARD_LTDC_GCR_VSPOL 0 /* !LTDC_GCR_VSPOL */
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/* Horicontal Sync Polarity */
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#define BOARD_LTDC_GCR_HSPOL 0 /* !LTDC_GCR_HSPOL */
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/* GPIO pinset */
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#define GPIO_LTDC_PINS 24 /* 24-bit display */
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#define GPIO_LTDC_R0 GPIO_LTDC_R0_3
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#define GPIO_LTDC_R1 GPIO_LTDC_R1_3
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#define GPIO_LTDC_R2 GPIO_LTDC_R2_4
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#define GPIO_LTDC_R3 GPIO_LTDC_R3_3
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#define GPIO_LTDC_R4 GPIO_LTDC_R4_4
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#define GPIO_LTDC_R5 GPIO_LTDC_R5_4
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#define GPIO_LTDC_R6 GPIO_LTDC_R6_4
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#define GPIO_LTDC_R7 GPIO_LTDC_R7_3
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#define GPIO_LTDC_G0 GPIO_LTDC_G0_2
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#define GPIO_LTDC_G1 GPIO_LTDC_G1_2
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#define GPIO_LTDC_G2 GPIO_LTDC_G2_3
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#define GPIO_LTDC_G3 GPIO_LTDC_G3_4
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#define GPIO_LTDC_G4 GPIO_LTDC_G4_3
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#define GPIO_LTDC_G5 GPIO_LTDC_G5_3
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#define GPIO_LTDC_G6 GPIO_LTDC_G6_3
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#define GPIO_LTDC_G7 GPIO_LTDC_G7_3
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#define GPIO_LTDC_B0 GPIO_LTDC_B0_1
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#define GPIO_LTDC_B1 GPIO_LTDC_B1_2
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#define GPIO_LTDC_B2 GPIO_LTDC_B2_3
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#define GPIO_LTDC_B3 GPIO_LTDC_B3_3
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#define GPIO_LTDC_B4 GPIO_LTDC_B4_4
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#define GPIO_LTDC_B5 GPIO_LTDC_B5_3
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#define GPIO_LTDC_B6 GPIO_LTDC_B6_3
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#define GPIO_LTDC_B7 GPIO_LTDC_B7_3
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#define GPIO_LTDC_VSYNC GPIO_LTDC_VSYNC_2
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#define GPIO_LTDC_HSYNC GPIO_LTDC_HSYNC_2
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#define GPIO_LTDC_DE GPIO_LTDC_DE_3
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#define GPIO_LTDC_CLK GPIO_LTDC_CLK_3
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#endif /* __CONFIG_STM32F746G_DISCO_INCLUDE_BOARD_H */
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