e5dfd805e6
Add support for LPC40xx family chips
* Corrected a few peripheral definitions and pin functions for the LPC17xx family.
Added configuration options, chip definitions, and additional pin functions for the LPC40xx family.
Added board configurations for Embedded Artists LPC4088 Quickstart board and LPC4088 Developer's kit. These configurations are still something of a work in progress. In particular, the LCD functionality is untested.
* First pass rename in *.c and *.h files.
* Renamed LPC17XX to LPC17XX_40XX in config files
* Rplaced LPC17xx with LPC17xx/LPC40xx in .c files
* Replaced LPC17xx with LPC17xx/LPC40xx in .h files
* Updated some documentation
* Working on moving directories
* moved arch/arm/src/lpc17xx and arch/arm/include/lpc17xx to lpc17xx_40xx
* Renamed LPC17_* constants / configuration options to LPC17_40_*
* Updated chip family name defines
* Renamed some chip-specific files
* Updated references to renamed files
* Updated references to lpc17_ to lpc17_40_
* Renamed source files from lpc17_* to lpc17_40_*
* Clean up white space
Approved-by: Gregory Nutt <gnutt@nuttx.org>
956 lines
23 KiB
Plaintext
956 lines
23 KiB
Plaintext
#
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# For a description of the syntax of this configuration file,
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# see the file kconfig-language.txt in the NuttX tools repository.
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#
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if ARCH_ARM
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comment "ARM Options"
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choice
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prompt "ARM MCU selection"
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default ARCH_CHIP_STM32
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config ARCH_CHIP_A1X
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bool "Allwinner A1X"
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select ARCH_CORTEXA8
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select ARCH_HAVE_FPU
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select ARCH_HAVE_IRQPRIO
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select ARCH_HAVE_LOWVECTORS
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select ARCH_HAVE_FETCHADD
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select ARCH_HAVE_SDRAM
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select BOOT_RUNFROMSDRAM
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select ARCH_HAVE_ADDRENV
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select ARCH_NEED_ADDRENV_MAPPING
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---help---
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Allwinner A1X family: A10, A10S (A12), A13 (ARM Cortex-A8)
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config ARCH_CHIP_AM335X
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bool "TI AM335X"
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select ARCH_CORTEXA8
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select ARCH_HAVE_FPU
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select ARCH_HAVE_IRQPRIO
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select ARCH_HAVE_LOWVECTORS
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select ARCH_HAVE_FETCHADD
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select ARCH_HAVE_SDRAM
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select BOOT_RUNFROMSDRAM
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select ARCH_HAVE_ADDRENV
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select ARCH_NEED_ADDRENV_MAPPING
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---help---
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TI AM335X family: AM3356, AM3357, AM3358, AM3359 (ARM Cortex-A8)
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config ARCH_CHIP_C5471
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bool "TMS320 C5471"
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select ARCH_ARM7TDMI
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select ARCH_HAVE_LOWVECTORS
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select OTHER_UART_SERIALDRIVER
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---help---
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TI TMS320 C5471, A180, or DA180 (ARM7TDMI)
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config ARCH_CHIP_DM320
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bool "TMS320 DM320"
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select ARCH_ARM926EJS
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select ARCH_HAVE_LOWVECTORS
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---help---
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TI DMS320 DM320 (ARM926EJS)
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config ARCH_CHIP_EFM32
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bool "Energy Micro EFM32"
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select ARCH_HAVE_SPI_BITORDER
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select ARCH_HAVE_FETCHADD
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---help---
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Energy Micro EFM32 microcontrollers (ARM Cortex-M).
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config ARCH_CHIP_IMX1
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bool "NXP/Freescale iMX.1"
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select ARCH_ARM920T
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select ARCH_HAVE_HEAP2
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select ARCH_HAVE_LOWVECTORS
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---help---
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Freescale iMX.1 architectures (ARM920T)
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config ARCH_CHIP_IMX6
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bool "NXP/Freescale iMX.6"
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select ARCH_CORTEXA9
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select ARMV7A_HAVE_L2CC_PL310
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select ARCH_HAVE_FPU
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select ARCH_HAVE_TRUSTZONE
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select ARCH_HAVE_LOWVECTORS
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select ARCH_HAVE_FETCHADD
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select ARCH_HAVE_SDRAM
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select BOOT_RUNFROMSDRAM
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select ARCH_HAVE_ADDRENV
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select ARCH_NEED_ADDRENV_MAPPING
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---help---
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Freescale iMX.6 architectures (Cortex-A9)
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config ARCH_CHIP_IMXRT
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bool "NXP/Freescale iMX.RT"
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select ARCH_CORTEXM7
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select ARCH_HAVE_MPU
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select ARCH_HAVE_FETCHADD
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select ARCH_HAVE_RAMFUNCS
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select ARCH_HAVE_TICKLESS
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select ARCH_HAVE_I2CRESET
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select ARCH_HAVE_SPI_CS_CONTROL
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select ARM_HAVE_MPU_UNIFIED
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select ARMV7M_HAVE_STACKCHECK
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---help---
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NXP i.MX RT (ARM Cortex-M7) architectures
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config ARCH_CHIP_KINETIS
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bool "NXP/Freescale Kinetis"
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select ARCH_CORTEXM4
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select ARCH_HAVE_MPU
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select ARM_HAVE_MPU_UNIFIED
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select ARCH_HAVE_FPU
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select ARCH_HAVE_FETCHADD
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select ARCH_HAVE_RAMFUNCS
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select ARCH_HAVE_I2CRESET
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---help---
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Freescale Kinetis Architectures (ARM Cortex-M4)
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config ARCH_CHIP_KL
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bool "NXP/Freescale Kinetis L"
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select ARCH_CORTEXM0
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---help---
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Freescale Kinetis L Architectures (ARM Cortex-M0+)
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config ARCH_CHIP_LC823450
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bool "ON Semiconductor LC823450"
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select ARCH_CORTEXM3
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select ARCH_HAVE_MPU
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select ARCH_HAVE_HEAPCHECK
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select ARCH_HAVE_MULTICPU
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select ARCH_HAVE_I2CRESET
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select ARCH_GLOBAL_IRQDISABLE
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---help---
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ON Semiconductor LC823450 architectures (ARM dual Cortex-M3)
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config ARCH_CHIP_LM
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bool "TI/Luminary Stellaris"
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select ARCH_HAVE_MPU
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select ARM_HAVE_MPU_UNIFIED
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---help---
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TI/Luminary Stellaris LMS3 and LM4F architectures (ARM Cortex-M3/4)
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config ARCH_CHIP_LPC11XX
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bool "NXP LPC11xx"
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select ARCH_CORTEXM0
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---help---
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NXP LPC11xx architectures (ARM Cortex-M0)
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config ARCH_CHIP_LPC17XX_40XX
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bool "NXP LPC17xx/LPC40xx"
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select ARCH_HAVE_MPU
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select ARM_HAVE_MPU_UNIFIED
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select ARCH_HAVE_FETCHADD
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select ARMV7M_HAVE_STACKCHECK
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---help---
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NXP LPC17xx & LPC40xx architectures (ARM Cortex-M3/4)
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config ARCH_CHIP_LPC214X
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bool "NXP LPC214x"
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select ARCH_ARM7TDMI
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select ARCH_HAVE_LOWVECTORS
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---help---
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NXP LPC2145x architectures (ARM7TDMI)
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config ARCH_CHIP_LPC2378
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bool "NXP LPC2378"
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select ARCH_ARM7TDMI
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select ARCH_HAVE_LOWVECTORS
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---help---
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NXP LPC2145x architectures (ARM7TDMI)
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config ARCH_CHIP_LPC31XX
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bool "NXP LPC31XX"
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select ARCH_ARM926EJS
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select ARCH_HAVE_LOWVECTORS
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---help---
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NPX LPC31XX architectures (ARM926EJS).
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config ARCH_CHIP_LPC43XX
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bool "NXP LPC43XX"
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select ARCH_CORTEXM4
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select ARCH_HAVE_MPU
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select ARM_HAVE_MPU_UNIFIED
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select ARCH_HAVE_FPU
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select ARCH_HAVE_FETCHADD
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---help---
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NPX LPC43XX architectures (ARM Cortex-M4).
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config ARCH_CHIP_LPC54XX
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bool "NXP LPC54XX"
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select ARCH_CORTEXM4
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select ARCH_HAVE_MPU
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select ARM_HAVE_MPU_UNIFIED
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select ARCH_HAVE_FPU
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select ARCH_HAVE_FETCHADD
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---help---
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NPX LPC54XX architectures (ARM Cortex-M4).
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config ARCH_CHIP_MAX326XX
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bool "Maxim Integrated MAX326XX"
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select ARCH_HAVE_FETCHADD
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---help---
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Maxim Integrated MAX326XX microcontrollers (ARM Cortex-M4F).
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config ARCH_CHIP_MOXART
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bool "MoxART"
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select ARCH_ARM7TDMI
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select ARCH_HAVE_RESET
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select ARCH_HAVE_SERIAL_TERMIOS
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---help---
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MoxART family
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config ARCH_CHIP_NRF52
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bool "Nordic NRF52"
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select ARCH_CORTEXM4
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#select ARCH_HAVE_MPU
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#select ARM_HAVE_MPU_UNIFIED
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select ARCH_HAVE_FPU
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---help---
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Nordic NRF52 architectures (ARM Cortex-M4).
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config ARCH_CHIP_NUC1XX
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bool "Nuvoton NUC100/120"
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select ARCH_CORTEXM0
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---help---
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Nuvoton NUC100/120 architectures (ARM Cortex-M0).
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config ARCH_CHIP_SAMA5
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bool "Atmel SAMA5"
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select ARCH_CORTEXA5
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select ARCH_HAVE_FPU
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select ARCH_HAVE_IRQPRIO
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select ARCH_HAVE_LOWVECTORS
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select ARCH_HAVE_FETCHADD
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select ARCH_HAVE_I2CRESET
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select ARCH_HAVE_TICKLESS
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select ARCH_HAVE_ADDRENV
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select ARCH_NEED_ADDRENV_MAPPING
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---help---
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Atmel SAMA5 (ARM Cortex-A5)
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config ARCH_CHIP_SAMD2X
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bool "Microchip/Atmel SAMD2x"
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select ARCH_CORTEXM0
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---help---
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Microchip (formerly Atmel) SAMD2X (ARM Cortex-M0+)
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config ARCH_CHIP_SAML2X
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bool "Microchip/Atmel SAML2x"
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select ARCH_CORTEXM0
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---help---
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Microchip (formerly Atmel) SAML2X (ARM Cortex-M0+)
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config ARCH_CHIP_SAMD5X
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bool "Microchip SAMD5x"
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select ARCH_CORTEXM4
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---help---
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Microchip SAMD5X (ARM Cortex-M4)
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config ARCH_CHIP_SAME5X
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bool "Microchip SAME5x"
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select ARCH_CORTEXM4
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---help---
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Microchip SAME5x (ARM Cortex-M4)
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config ARCH_CHIP_SAM34
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bool "Atmel SAM3/SAM4"
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select ARCH_HAVE_MPU
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select ARM_HAVE_MPU_UNIFIED
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select ARCH_HAVE_FETCHADD
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select ARCH_HAVE_RAMFUNCS
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select ARMV7M_HAVE_STACKCHECK
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---help---
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Atmel SAM3 (ARM Cortex-M3) and SAM4 (ARM Cortex-M4) architectures
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config ARCH_CHIP_SAMV7
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bool "Atmel SAMV7"
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select ARCH_CORTEXM7
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select ARCH_HAVE_MPU
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select ARCH_HAVE_FETCHADD
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select ARCH_HAVE_RAMFUNCS
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select ARCH_HAVE_TICKLESS
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select ARCH_HAVE_I2CRESET
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select ARCH_HAVE_SPI_CS_CONTROL
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select ARM_HAVE_MPU_UNIFIED
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select ARMV7M_HAVE_STACKCHECK
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---help---
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Atmel SAMV7 (ARM Cortex-M7) architectures
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config ARCH_CHIP_SIMPLELINK
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bool "TI SimpleLink"
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select ARCH_HAVE_MPU
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select ARM_HAVE_MPU_UNIFIED
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select ARCH_HAVE_FETCHADD
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depends on EXPERIMENTAL
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---help---
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TI SimpleLink CCxxx architectures (ARM Cortex-M3 or M4)
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config ARCH_CHIP_STM32
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bool "STMicro STM32 F1/F2/F3/F4/L1"
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select ARCH_HAVE_MPU
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select ARCH_HAVE_FETCHADD
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select ARCH_HAVE_I2CRESET
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select ARCH_HAVE_HEAPCHECK
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select ARCH_HAVE_PROGMEM
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select ARCH_HAVE_SPI_BITORDER
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select ARCH_HAVE_TICKLESS
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select ARCH_HAVE_TIMEKEEPING
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select ARM_HAVE_MPU_UNIFIED
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select ARMV7M_HAVE_STACKCHECK
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---help---
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STMicro STM32 architectures (ARM Cortex-M3/4).
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config ARCH_CHIP_STM32F0
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bool "STMicro STM32 F0"
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select ARCH_CORTEXM0
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---help---
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STMicro STM32F0 architectures (ARM Cortex-M0).
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config ARCH_CHIP_STM32L0
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bool "STMicro STM32 L0"
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select ARCH_CORTEXM0
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---help---
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STMicro STM32L0 architectures (ARM Cortex-M0).
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config ARCH_CHIP_STM32G0
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bool "STMicro STM32 G0"
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select ARCH_CORTEXM0
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---help---
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STMicro STM32G0 architectures (ARM Cortex-M0).
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config ARCH_CHIP_STM32F7
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bool "STMicro STM32 F7"
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select ARCH_CORTEXM7
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select ARCH_HAVE_MPU
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select ARCH_HAVE_FETCHADD
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select ARCH_HAVE_I2CRESET
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select ARCH_HAVE_HEAPCHECK
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select ARCH_HAVE_PROGMEM
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select ARCH_HAVE_SPI_BITORDER
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select ARM_HAVE_MPU_UNIFIED
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select ARMV7M_HAVE_STACKCHECK
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select ARCH_HAVE_TICKLESS
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select ARCH_HAVE_TIMEKEEPING
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---help---
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STMicro STM32 architectures (ARM Cortex-M7).
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config ARCH_CHIP_STM32H7
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bool "STMicro STM32 H7"
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select ARCH_CORTEXM7
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select ARCH_HAVE_MPU
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# select ARCH_HAVE_I2CRESET
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# select ARCH_HAVE_HEAPCHECK
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select ARCH_HAVE_SPI_BITORDER
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select ARM_HAVE_MPU_UNIFIED
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# select ARMV7M_HAVE_STACKCHECK
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---help---
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STMicro STM32H7 architectures (ARM Cortex-M7).
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BEWARE: This is a work-in-progress and not yet ready for general
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usage. See configs/nucleo-h743zi/README.txt for the current state
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of the port.
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config ARCH_CHIP_STM32L4
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bool "STMicro STM32 L4"
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select ARCH_CORTEXM4
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select ARCH_HAVE_MPU
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select ARCH_HAVE_FETCHADD
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select ARCH_HAVE_I2CRESET
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select ARCH_HAVE_HEAPCHECK
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select ARCH_HAVE_PROGMEM
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select ARCH_HAVE_SPI_BITORDER
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select ARCH_HAVE_TICKLESS
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select ARM_HAVE_MPU_UNIFIED
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select ARMV7M_HAVE_STACKCHECK
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---help---
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STMicro STM32 architectures (ARM Cortex-M4).
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config ARCH_CHIP_STR71X
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bool "STMicro STR71x"
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select ARCH_ARM7TDMI
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select ARCH_HAVE_LOWVECTORS
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---help---
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STMicro STR71x architectures (ARM7TDMI).
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config ARCH_CHIP_TMS570
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bool "TI TMS570"
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select ENDIAN_BIG
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select ARCH_HAVE_LOWVECTORS
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select ARCH_HAVE_FETCHADD
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select ARCH_HAVE_RAMFUNCS
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select ARMV7R_MEMINIT
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select ARMV7R_HAVE_DECODEFIQ
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---help---
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TI TMS570 family
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config ARCH_CHIP_TIVA
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bool "TI Tiva"
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select ARCH_HAVE_MPU
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select ARM_HAVE_MPU_UNIFIED
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select ARCH_HAVE_FETCHADD
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---help---
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TI Tiva TM4C architectures (ARM Cortex-M4)
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config ARCH_CHIP_XMC4
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bool "Infineon XMC4xxx"
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select ARCH_CORTEXM4
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select ARCH_HAVE_MPU
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select ARCH_HAVE_FETCHADD
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select ARCH_HAVE_RAMFUNCS
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select ARCH_HAVE_I2CRESET
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select ARM_HAVE_MPU_UNIFIED
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select ARMV7M_HAVE_STACKCHECK
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---help---
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Infineon XMC4xxx(ARM Cortex-M4) architectures
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config ARCH_CHIP_CXD56XX
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bool "Sony CXD56xx"
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select ARCH_CORTEXM4
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select ARCH_HAVE_MPU
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select ARM_HAVE_MPU_UNIFIED
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select ARCH_HAVE_FPU
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select ARCH_HAVE_HEAPCHECK
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select ARCH_HAVE_MULTICPU
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select ARCH_HAVE_SDIO if MMCSD
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---help---
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Sony CXD56XX (ARM Cortex-M4) architectures
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endchoice
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config ARCH_ARM7TDMI
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bool
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default n
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select ARCH_DCACHE
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select ARCH_ICACHE
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---help---
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The Arm7TDMI-S is an excellent workhorse processor capable of a wide
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array of applications. Traditionally used in mobile handsets, the
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processor is now broadly in many non-mobile applications.
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config ARCH_ARM920T
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bool
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default n
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select ARCH_DCACHE
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select ARCH_ICACHE
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select ARCH_HAVE_MMU
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select ARCH_USE_MMU
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---help---
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The ARM9 processor family is built around the ARM9TDMI processor and
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incorporates the 16-bit Thumb instruction set. The ARM9 Thumb family
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includes the ARM920T and ARM922T cached processor macrocells:
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- Dual 16k caches for applications running Symbian OS, Palm OS,
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Linux and Windows CE,
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- Dual 8k caches for applications running Symbian OS, Palm OS, Linux
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and Windows CE Applications
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config ARCH_ARM926EJS
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bool
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default n
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select ARCH_DCACHE
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select ARCH_ICACHE
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select ARCH_HAVE_MMU
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select ARCH_USE_MMU
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---help---
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Arm926EJ-S is the entry point processor capable of supporting full
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Operating Systems including Linux, WindowsCE, and Symbian.
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The ARM9E processor family enables single processor solutions for
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microcontroller, DSP and Java applications. The ARM9E family of
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products are DSP-enhanced 32-bit RISC processors, for applications
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requiring a mix of DSP and microcontroller performance. The family
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includes the ARM926EJ-S, ARM946E-S, ARM966E-S, and ARM968E-S
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processor macrocells. They include signal processing extensions to
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enhance 16-bit fixed point performance using a single-cycle 32 x 16
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multiply-accumulate (MAC) unit, and implement the 16-bit Thumb
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instruction set. The ARM926EJ-S processor also includes ARM Jazelle
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technology which enables the direct execution of Java bytecodes in
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hardware.
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config ARCH_ARM1136J
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bool
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default n
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select ARCH_DCACHE
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select ARCH_ICACHE
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select ARCH_HAVE_MMU
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select ARCH_USE_MMU
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---help---
|
|
Arm1136J(F)-S is very similar to Arm926EJ-S, but includes an
|
|
extended pipeline, basic SIMD (Single Instruction Multiple Data)
|
|
instructions, and improved frequency and performance.
|
|
|
|
config ARCH_ARM1156T2
|
|
bool
|
|
default n
|
|
select ARCH_DCACHE
|
|
select ARCH_ICACHE
|
|
select ARCH_HAVE_MMU
|
|
select ARCH_USE_MMU
|
|
---help---
|
|
Arm1156T2(F)-S is the highest-performance processor in the real-time
|
|
Classic Arm family.
|
|
|
|
config ARCH_ARM1176JZ
|
|
bool
|
|
default n
|
|
select ARCH_DCACHE
|
|
select ARCH_ICACHE
|
|
select ARCH_HAVE_MMU
|
|
select ARCH_USE_MMU
|
|
---help---
|
|
Arm1176JZ(F)-S is the highest-performance single-core processor in
|
|
the Classic Arm family. It also introduced TrustZone technology to
|
|
enable secure execution outside of the reach of malicious code.
|
|
|
|
config ARCH_CORTEXM0
|
|
bool
|
|
default n
|
|
select ARCH_HAVE_IRQPRIO
|
|
select ARCH_HAVE_RESET
|
|
select ARCH_HAVE_HARDFAULT_DEBUG
|
|
|
|
config ARCH_CORTEXM23
|
|
bool
|
|
default n
|
|
|
|
config ARCH_ARMV7M
|
|
bool
|
|
default n
|
|
|
|
config ARCH_CORTEXM3
|
|
bool
|
|
default n
|
|
select ARCH_ARMV7M
|
|
select ARCH_HAVE_IRQPRIO
|
|
select ARCH_HAVE_IRQTRIGGER
|
|
select ARCH_HAVE_RAMVECTORS
|
|
select ARCH_HAVE_LAZYFPU
|
|
select ARCH_HAVE_HIPRI_INTERRUPT
|
|
select ARCH_HAVE_RESET
|
|
select ARCH_HAVE_TESTSET
|
|
select ARCH_HAVE_HARDFAULT_DEBUG
|
|
select ARCH_HAVE_MEMFAULT_DEBUG
|
|
|
|
config ARCH_CORTEXM33
|
|
bool
|
|
default n
|
|
|
|
config ARCH_CORTEXM4
|
|
bool
|
|
default n
|
|
select ARCH_ARMV7M
|
|
select ARCH_HAVE_IRQPRIO
|
|
select ARCH_HAVE_IRQTRIGGER
|
|
select ARCH_HAVE_RAMVECTORS
|
|
select ARCH_HAVE_LAZYFPU
|
|
select ARCH_HAVE_HIPRI_INTERRUPT
|
|
select ARCH_HAVE_RESET
|
|
select ARCH_HAVE_TESTSET
|
|
select ARCH_HAVE_HARDFAULT_DEBUG
|
|
select ARCH_HAVE_MEMFAULT_DEBUG
|
|
|
|
config ARCH_CORTEXM7
|
|
bool
|
|
default n
|
|
select ARCH_ARMV7M
|
|
select ARCH_HAVE_FPU
|
|
select ARCH_HAVE_IRQPRIO
|
|
select ARCH_HAVE_IRQTRIGGER
|
|
select ARCH_HAVE_RAMVECTORS
|
|
select ARCH_HAVE_LAZYFPU
|
|
select ARCH_HAVE_HIPRI_INTERRUPT
|
|
select ARCH_HAVE_RESET
|
|
select ARCH_HAVE_TESTSET
|
|
select ARCH_HAVE_HARDFAULT_DEBUG
|
|
select ARCH_HAVE_MEMFAULT_DEBUG
|
|
|
|
config ARCH_ARMV7A
|
|
bool
|
|
default n
|
|
|
|
config ARCH_CORTEXA5
|
|
bool
|
|
default n
|
|
select ARCH_ARMV7A
|
|
select ARCH_DCACHE
|
|
select ARCH_ICACHE
|
|
select ARCH_HAVE_MMU
|
|
select ARCH_USE_MMU
|
|
select ARCH_HAVE_TESTSET
|
|
|
|
config ARCH_CORTEXA7
|
|
bool
|
|
default n
|
|
select ARCH_ARMV7A
|
|
select ARCH_DCACHE
|
|
select ARCH_ICACHE
|
|
select ARCH_HAVE_MMU
|
|
select ARCH_USE_MMU
|
|
select ARCH_HAVE_TESTSET
|
|
|
|
config ARCH_CORTEXA8
|
|
bool
|
|
default n
|
|
select ARCH_ARMV7A
|
|
select ARCH_DCACHE
|
|
select ARCH_ICACHE
|
|
select ARCH_HAVE_MMU
|
|
select ARCH_USE_MMU
|
|
select ARCH_HAVE_TESTSET
|
|
|
|
config ARCH_CORTEXA9
|
|
bool
|
|
default n
|
|
select ARCH_ARMV7A
|
|
select ARCH_DCACHE
|
|
select ARCH_ICACHE
|
|
select ARCH_HAVE_MMU
|
|
select ARCH_USE_MMU
|
|
select ARCH_HAVE_TESTSET
|
|
|
|
config ARCH_ARMV7R
|
|
bool
|
|
default n
|
|
|
|
config ARCH_CORTEXR4
|
|
bool
|
|
default n
|
|
select ARCH_ARMV7R
|
|
select ARCH_DCACHE
|
|
select ARCH_ICACHE
|
|
select ARCH_HAVE_MPU
|
|
select ARCH_HAVE_TESTSET
|
|
|
|
config ARCH_CORTEXR5
|
|
bool
|
|
default n
|
|
select ARCH_ARMV7R
|
|
select ARCH_DCACHE
|
|
select ARCH_ICACHE
|
|
select ARCH_HAVE_MPU
|
|
select ARCH_HAVE_TESTSET
|
|
|
|
config ARCH_CORTEXR7
|
|
bool
|
|
default n
|
|
select ARCH_ARMV7R
|
|
select ARCH_DCACHE
|
|
select ARCH_ICACHE
|
|
select ARCH_HAVE_MPU
|
|
select ARCH_HAVE_TESTSET
|
|
|
|
config ARCH_FAMILY
|
|
string
|
|
default "arm" if ARCH_ARM7TDMI || ARCH_ARM926EJS || ARCH_ARM920T
|
|
default "armv6-m" if ARCH_CORTEXM0
|
|
default "armv7-a" if ARCH_ARMV7A
|
|
default "armv7-m" if ARCH_ARMV7M
|
|
default "armv7-r" if ARCH_ARMV7R
|
|
|
|
config ARCH_CHIP
|
|
string
|
|
default "a1x" if ARCH_CHIP_A1X
|
|
default "am335x" if ARCH_CHIP_AM335X
|
|
default "c5471" if ARCH_CHIP_C5471
|
|
default "dm320" if ARCH_CHIP_DM320
|
|
default "efm32" if ARCH_CHIP_EFM32
|
|
default "imx1" if ARCH_CHIP_IMX1
|
|
default "imx6" if ARCH_CHIP_IMX6
|
|
default "imxrt" if ARCH_CHIP_IMXRT
|
|
default "kinetis" if ARCH_CHIP_KINETIS
|
|
default "kl" if ARCH_CHIP_KL
|
|
default "lc823450" if ARCH_CHIP_LC823450
|
|
default "tiva" if ARCH_CHIP_LM || ARCH_CHIP_TIVA ||ARCH_CHIP_SIMPLELINK
|
|
default "lpc11xx" if ARCH_CHIP_LPC11XX
|
|
default "lpc17xx_40xx" if ARCH_CHIP_LPC17XX_40XX
|
|
default "lpc214x" if ARCH_CHIP_LPC214X
|
|
default "lpc2378" if ARCH_CHIP_LPC2378
|
|
default "lpc31xx" if ARCH_CHIP_LPC31XX
|
|
default "lpc43xx" if ARCH_CHIP_LPC43XX
|
|
default "lpc54xx" if ARCH_CHIP_LPC54XX
|
|
default "max326xx" if ARCH_CHIP_MAX326XX
|
|
default "moxart" if ARCH_CHIP_MOXART
|
|
default "nrf52" if ARCH_CHIP_NRF52
|
|
default "nuc1xx" if ARCH_CHIP_NUC1XX
|
|
default "sama5" if ARCH_CHIP_SAMA5
|
|
default "samd2l2" if ARCH_CHIP_SAMD2X || ARCH_CHIP_SAML2X
|
|
default "samd5e5" if ARCH_CHIP_SAMD5X || ARCH_CHIP_SAME5X
|
|
default "sam34" if ARCH_CHIP_SAM34
|
|
default "samv7" if ARCH_CHIP_SAMV7
|
|
default "stm32" if ARCH_CHIP_STM32
|
|
default "stm32f0l0g0" if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0
|
|
default "stm32f7" if ARCH_CHIP_STM32F7
|
|
default "stm32h7" if ARCH_CHIP_STM32H7
|
|
default "stm32l4" if ARCH_CHIP_STM32L4
|
|
default "str71x" if ARCH_CHIP_STR71X
|
|
default "tms570" if ARCH_CHIP_TMS570
|
|
default "xmc4" if ARCH_CHIP_XMC4
|
|
default "cxd56xx" if ARCH_CHIP_CXD56XX
|
|
|
|
config ARCH_HAVE_TRUSTZONE
|
|
bool
|
|
default n
|
|
---help---
|
|
Automatically selected to indicate that the ARM CPU supports
|
|
TrustZone.
|
|
|
|
choice
|
|
prompt "TrustZone Configuration"
|
|
default ARCH_TRUSTZONE_SECURE
|
|
depends on ARCH_HAVE_TRUSTZONE
|
|
|
|
config ARCH_TRUSTZONE_SECURE
|
|
bool "All CPUs operate secure state"
|
|
|
|
config ARCH_TRUSTZONE_NONSECURE
|
|
bool "All CPUs operate non-secure state"
|
|
depends on EXPERIMENTAL
|
|
|
|
config ARCH_TRUSTZONE_BOTH
|
|
bool "CPUs operate in both secure and non-secure states"
|
|
depends on EXPERIMENTAL
|
|
|
|
endchoice # TrustZone Configuration
|
|
|
|
config ARM_THUMB
|
|
bool
|
|
default n
|
|
depends on ARCH_ARMV7A
|
|
|
|
config ARM_HAVE_MPU_UNIFIED
|
|
bool
|
|
default n
|
|
---help---
|
|
Automatically selected to indicate that the CPU supports a
|
|
unified MPU for both instruction and data addresses.
|
|
|
|
config ARM_MPU
|
|
bool "MPU support"
|
|
default n
|
|
depends on ARCH_HAVE_MPU
|
|
select ARCH_USE_MPU
|
|
---help---
|
|
Build in support for the ARM Cortex-M3/4/7 Memory Protection Unit (MPU).
|
|
Check your chip specifications first; not all Cortex-M3/4/7 chips
|
|
support the MPU.
|
|
|
|
config ARM_MPU_NREGIONS
|
|
int "Number of MPU regions"
|
|
default 16 if ARCH_CORTEXM7
|
|
default 8 if !ARCH_CORTEXM7
|
|
depends on ARM_MPU
|
|
---help---
|
|
This is the number of protection regions supported by the MPU.
|
|
|
|
config ARCH_HAVE_LOWVECTORS
|
|
bool
|
|
|
|
config ARCH_LOWVECTORS
|
|
bool "Vectors in low memory"
|
|
default n
|
|
depends on ARCH_HAVE_LOWVECTORS
|
|
---help---
|
|
Support ARM vectors in low memory.
|
|
|
|
config ARCH_ROMPGTABLE
|
|
bool "ROM page table"
|
|
default n
|
|
depends on ARCH_USE_MMU
|
|
---help---
|
|
Support a fixed memory mapping use a (read-only) page table in
|
|
ROM/FLASH.
|
|
|
|
config ARCH_HAVE_HARDFAULT_DEBUG
|
|
bool
|
|
default n
|
|
|
|
config DEBUG_HARDFAULT_ALERT
|
|
bool "Hard-Fault Alert Debug"
|
|
default n
|
|
depends on ARCH_HAVE_HARDFAULT_DEBUG && DEBUG_ALERT
|
|
---help---
|
|
Enables debug alert output to the SYSLOG when a hard fault
|
|
occurs. This output is sometimes helpful when debugging difficult
|
|
hard fault problems.
|
|
|
|
config DEBUG_HARDFAULT_INFO
|
|
bool "Hard-Fault Informational Output"
|
|
default n
|
|
depends on ARCH_HAVE_HARDFAULT_DEBUG && DEBUG_INFO
|
|
---help---
|
|
Enables informational alert output to the SYSLOG when a hard fault
|
|
occurs. This output is sometimes helpful when debugging difficult
|
|
hard fault problems but may be more than you want to see in some
|
|
cases.
|
|
|
|
config ARCH_HAVE_MEMFAULT_DEBUG
|
|
bool
|
|
default n
|
|
|
|
config DEBUG_MEMFAULT
|
|
bool "Verbose Mem-Fault Debug"
|
|
default n
|
|
depends on ARCH_HAVE_MEMFAULT_DEBUG && DEBUG_ALERT && ARCH_USE_MPU
|
|
---help---
|
|
Enables verbose debug output when a mem fault is occurs. This verbose
|
|
output is sometimes helpful when debugging difficult mem fault problems,
|
|
but may be more than you typically want to see.
|
|
|
|
config ARM_SEMIHOSTING_SYSLOG
|
|
bool "Semihosting SYSLOG support"
|
|
select ARCH_SYSLOG
|
|
---help---
|
|
Enable hooks to support semihosting syslog output.
|
|
|
|
config ARM_SEMIHOSTING_HOSTFS
|
|
bool "Semihosting HostFS"
|
|
depends on FS_HOSTFS
|
|
---help---
|
|
Mount HostFS through semihosting.
|
|
|
|
config ARM_LWL_CONSOLE
|
|
bool "Lightweight Link Console Support"
|
|
default n
|
|
depends on DEV_CONSOLE && ARCH_CHIP_STM32
|
|
---help---
|
|
Use the lightweight link console which provides console over a
|
|
debug channel by means of shared memory. A terminal application
|
|
for openocd as the debugger is available in tools/ocdconsole.py.
|
|
|
|
Currently only available for STM32 architectures, but easily
|
|
added to other ARM architectures be addd up_low_console.c to the
|
|
architecture Make.defs file.
|
|
|
|
if ARCH_CORTEXM0
|
|
source arch/arm/src/armv6-m/Kconfig
|
|
endif
|
|
if ARCH_ARMV7A
|
|
source arch/arm/src/armv7-a/Kconfig
|
|
endif
|
|
if ARCH_ARMV7M
|
|
source arch/arm/src/armv7-m/Kconfig
|
|
endif
|
|
if ARCH_ARMV7R
|
|
source arch/arm/src/armv7-r/Kconfig
|
|
endif
|
|
if ARCH_ARM7TDMI || ARCH_ARM920T || ARCH_ARM926EJS || ARCH_ARM1136J || ARCH_ARM1156T2 || ARCH_ARM1176JZ
|
|
source arch/arm/src/arm/Kconfig
|
|
endif
|
|
if ARCH_CHIP_A1X
|
|
source arch/arm/src/a1x/Kconfig
|
|
endif
|
|
if ARCH_CHIP_AM335X
|
|
source arch/arm/src/am335x/Kconfig
|
|
endif
|
|
if ARCH_CHIP_C5471
|
|
source arch/arm/src/c5471/Kconfig
|
|
endif
|
|
if ARCH_CHIP_DM320
|
|
source arch/arm/src/dm320/Kconfig
|
|
endif
|
|
if ARCH_CHIP_EFM32
|
|
source arch/arm/src/efm32/Kconfig
|
|
endif
|
|
if ARCH_CHIP_IMX1
|
|
source arch/arm/src/imx1/Kconfig
|
|
endif
|
|
if ARCH_CHIP_IMX6
|
|
source arch/arm/src/imx6/Kconfig
|
|
endif
|
|
if ARCH_CHIP_IMXRT
|
|
source arch/arm/src/imxrt/Kconfig
|
|
endif
|
|
if ARCH_CHIP_KINETIS
|
|
source arch/arm/src/kinetis/Kconfig
|
|
endif
|
|
if ARCH_CHIP_KL
|
|
source arch/arm/src/kl/Kconfig
|
|
endif
|
|
if ARCH_CHIP_LC823450
|
|
source arch/arm/src/lc823450/Kconfig
|
|
endif
|
|
if ARCH_CHIP_LM || ARCH_CHIP_TIVA || ARCH_CHIP_SIMPLELINK
|
|
source arch/arm/src/tiva/Kconfig
|
|
endif
|
|
if ARCH_CHIP_LPC11XX
|
|
source arch/arm/src/lpc11xx/Kconfig
|
|
endif
|
|
if ARCH_CHIP_LPC17XX_40XX
|
|
source arch/arm/src/lpc17xx_40xx/Kconfig
|
|
endif
|
|
if ARCH_CHIP_LPC214X
|
|
source arch/arm/src/lpc214x/Kconfig
|
|
endif
|
|
if ARCH_CHIP_LPC2378
|
|
source arch/arm/src/lpc2378/Kconfig
|
|
endif
|
|
if ARCH_CHIP_LPC31XX
|
|
source arch/arm/src/lpc31xx/Kconfig
|
|
endif
|
|
if ARCH_CHIP_LPC43XX
|
|
source arch/arm/src/lpc43xx/Kconfig
|
|
endif
|
|
if ARCH_CHIP_LPC54XX
|
|
source arch/arm/src/lpc54xx/Kconfig
|
|
endif
|
|
if ARCH_CHIP_MAX326XX
|
|
source arch/arm/src/max326xx/Kconfig
|
|
endif
|
|
if ARCH_CHIP_MOXART
|
|
source arch/arm/src/moxart/Kconfig
|
|
endif
|
|
if ARCH_CHIP_NRF52
|
|
source arch/arm/src/nrf52/Kconfig
|
|
endif
|
|
if ARCH_CHIP_NUC1XX
|
|
source arch/arm/src/nuc1xx/Kconfig
|
|
endif
|
|
if ARCH_CHIP_SAMA5
|
|
source arch/arm/src/sama5/Kconfig
|
|
endif
|
|
if ARCH_CHIP_SAMD2X || ARCH_CHIP_SAML2X
|
|
source arch/arm/src/samd2l2/Kconfig
|
|
endif
|
|
if ARCH_CHIP_SAMD5X || ARCH_CHIP_SAME5X
|
|
source arch/arm/src/samd5e5/Kconfig
|
|
endif
|
|
if ARCH_CHIP_SAM34
|
|
source arch/arm/src/sam34/Kconfig
|
|
endif
|
|
if ARCH_CHIP_SAMV7
|
|
source arch/arm/src/samv7/Kconfig
|
|
endif
|
|
if ARCH_CHIP_STM32
|
|
source arch/arm/src/stm32/Kconfig
|
|
endif
|
|
if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0
|
|
source arch/arm/src/stm32f0l0g0/Kconfig
|
|
endif
|
|
if ARCH_CHIP_STM32F7
|
|
source arch/arm/src/stm32f7/Kconfig
|
|
endif
|
|
if ARCH_CHIP_STM32H7
|
|
source arch/arm/src/stm32h7/Kconfig
|
|
endif
|
|
if ARCH_CHIP_STM32L4
|
|
source arch/arm/src/stm32l4/Kconfig
|
|
endif
|
|
if ARCH_CHIP_STR71X
|
|
source arch/arm/src/str71x/Kconfig
|
|
endif
|
|
if ARCH_CHIP_TMS570
|
|
source arch/arm/src/tms570/Kconfig
|
|
endif
|
|
if ARCH_CHIP_XMC4
|
|
source arch/arm/src/xmc4/Kconfig
|
|
endif
|
|
if ARCH_CHIP_CXD56XX
|
|
source arch/arm/src/cxd56xx/Kconfig
|
|
endif
|
|
|
|
endif # ARCH_ARM
|