e5dfd805e6
Add support for LPC40xx family chips
* Corrected a few peripheral definitions and pin functions for the LPC17xx family.
Added configuration options, chip definitions, and additional pin functions for the LPC40xx family.
Added board configurations for Embedded Artists LPC4088 Quickstart board and LPC4088 Developer's kit. These configurations are still something of a work in progress. In particular, the LCD functionality is untested.
* First pass rename in *.c and *.h files.
* Renamed LPC17XX to LPC17XX_40XX in config files
* Rplaced LPC17xx with LPC17xx/LPC40xx in .c files
* Replaced LPC17xx with LPC17xx/LPC40xx in .h files
* Updated some documentation
* Working on moving directories
* moved arch/arm/src/lpc17xx and arch/arm/include/lpc17xx to lpc17xx_40xx
* Renamed LPC17_* constants / configuration options to LPC17_40_*
* Updated chip family name defines
* Renamed some chip-specific files
* Updated references to renamed files
* Updated references to lpc17_ to lpc17_40_
* Renamed source files from lpc17_* to lpc17_40_*
* Clean up white space
Approved-by: Gregory Nutt <gnutt@nuttx.org>
637 lines
20 KiB
C
637 lines
20 KiB
C
/****************************************************************************
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* arch/arm/src/lpc17xx_40xx/lpc17_40_pwm.c
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*
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* Copyright (C) 2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <assert.h>
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#include <errno.h>
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#include <debug.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <nuttx/drivers/pwm.h>
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#include <arch/board/board.h>
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#include "up_internal.h"
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#include "up_arch.h"
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#include "chip.h"
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#include "hardware/lpc17_40_syscon.h"
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#include "lpc17_40_pwm.h"
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#include "hardware/lpc176x_pinconfig.h"
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#include "lpc17_40_gpio.h"
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#include "lpc176x_gpio.h"
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/* This module then only compiles if there is at least one enabled timer
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* intended for use with the PWM upper half driver.
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*/
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#if defined(CONFIG_LPC17_40_PWM1)
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* PWM/Timer Definitions ****************************************************/
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/* The following definitions are used to identify the various time types */
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#define TIMTYPE_BASIC 0 /* Basic timers: TIM6-7 */
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#define TIMTYPE_GENERAL16 1 /* General 16-bit timers: TIM2-5 on F1 */
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#define TIMTYPE_COUNTUP16 2 /* General 16-bit count-up timers: TIM9-14 on F4 */
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#define TIMTYPE_GENERAL32 3 /* General 32-bit timers: TIM2-5 on F4 */
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#define TIMTYPE_ADVANCED 4 /* Advanced timers: TIM1-8 */
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#define TIMTYPE_TIM1 TIMTYPE_ADVANCED
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#define LER0_EN (1 << 0)
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#define LER1_EN (1 << 1)
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#define LER2_EN (1 << 2)
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#define LER3_EN (1 << 3)
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#define LER4_EN (1 << 4)
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#define LER5_EN (1 << 5)
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#define LER6_EN (1 << 6)
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#define PWMENA1 (1 << 9)
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#define PWMENA2 (1 << 10)
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#define PWMENA3 (1 << 11)
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#define PWMENA4 (1 << 12)
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#define PWMENA5 (1 << 13)
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#define PWMENA6 (1 << 14)
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#define TCR_CNT_EN (0x00000001)
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#define TCR_RESET (0x00000002)
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#define TCR_PWM_EN (0x00000008)
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/* Debug ********************************************************************/
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#ifdef CONFIG_DEBUG_PWM_INFO
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# define pwm_dumpgpio(p,m) stm32_dumpgpio(p,m)
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#else
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# define pwm_dumpgpio(p,m)
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#endif
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/* This structure represents the state of one PWM timer */
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struct lpc17_40_pwmtimer_s
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{
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FAR const struct pwm_ops_s *ops; /* PWM operations */
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uint8_t timid; /* Timer ID {0,...,7} */
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uint8_t channel; /* Timer output channel: {1,..4} */
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uint8_t timtype; /* See the TIMTYPE_* definitions */
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uint32_t base; /* The base address of the timer */
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uint32_t pincfg; /* Output pin configuration */
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uint32_t pclk; /* The frequency of the peripheral clock
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* that drives the timer module. */
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};
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/****************************************************************************
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* Static Function Prototypes
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****************************************************************************/
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/* Register access */
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static uint32_t pwm_getreg(struct lpc17_40_pwmtimer_s *priv, int offset);
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static void pwm_putreg(struct lpc17_40_pwmtimer_s *priv, int offset, uint32_t value);
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#ifdef CONFIG_DEBUG_PWM_INFO
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static void pwm_dumpregs(struct lpc17_40_pwmtimer_s *priv, FAR const char *msg);
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#else
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# define pwm_dumpregs(priv,msg)
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#endif
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/* Timer management */
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static int pwm_timer(FAR struct lpc17_40_pwmtimer_s *priv,
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FAR const struct pwm_info_s *info);
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/* PWM driver methods */
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static int pwm_setup(FAR struct pwm_lowerhalf_s *dev);
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static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev);
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static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
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FAR const struct pwm_info_s *info);
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static int pwm_stop(FAR struct pwm_lowerhalf_s *dev);
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static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev,
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int cmd, unsigned long arg);
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* This is the list of lower half PWM driver methods used by the upper half driver */
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static const struct pwm_ops_s g_pwmops =
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{
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.setup = pwm_setup,
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.shutdown = pwm_shutdown,
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.start = pwm_start,
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.stop = pwm_stop,
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.ioctl = pwm_ioctl,
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};
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#ifdef CONFIG_LPC17_40_PWM1
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static struct lpc17_40_pwmtimer_s g_pwm1dev =
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{
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.ops = &g_pwmops,
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.timid = 1,
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.channel = CONFIG_LPC17_40_PWM1_PIN,
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.timtype = TIMTYPE_TIM1,
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.base = LPC17_40_PWM1_BASE,
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.pincfg = GPIO_PWM1p1_1,
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.pclk = (0x1 << 12),
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};
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#endif
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: pwm_getreg
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*
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* Description:
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* Read the value of an PWM timer register.
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*
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* Input Parameters:
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* priv - A reference to the PWM block status
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* offset - The offset to the register to read
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*
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* Returned Value:
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* The current contents of the specified register
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*
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****************************************************************************/
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static uint32_t pwm_getreg(struct lpc17_40_pwmtimer_s *priv, int offset)
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{
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return getreg32(priv->base + offset);
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}
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/****************************************************************************
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* Name: pwm_putreg
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*
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* Description:
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* Read the value of an PWM timer register.
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*
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* Input Parameters:
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* priv - A reference to the PWM block status
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* offset - The offset to the register to read
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static void pwm_putreg(struct lpc17_40_pwmtimer_s *priv, int offset, uint32_t value)
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{
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putreg32(value, priv->base + offset);
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}
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/****************************************************************************
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* Name: pwm_dumpregs
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*
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* Description:
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* Dump all timer registers.
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*
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* Input Parameters:
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* priv - A reference to the PWM block status
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#ifdef CONFIG_DEBUG_PWM_INFO
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static void pwm_dumpregs(struct lpc17_40_pwmtimer_s *priv, FAR const char *msg)
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{
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pwminfo("%s:\n", msg);
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pwminfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
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pwm_getreg(priv, LPC17_40_PWM_MR0_OFFSET),
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pwm_getreg(priv, LPC17_40_PWM_MR1_OFFSET),
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pwm_getreg(priv, LPC17_40_PWM_MR2_OFFSET),
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pwm_getreg(priv, LPC17_40_PWM_MR3_OFFSET));
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#if defined(CONFIG_LPC17_40_PWM1)
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if (priv->timtype == TIMTYPE_ADVANCED)
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{
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pwminfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
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pwm_getreg(priv, LPC17_40_PWM_MR0_OFFSET),
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pwm_getreg(priv, LPC17_40_PWM_MR1_OFFSET),
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pwm_getreg(priv, LPC17_40_PWM_MR2_OFFSET),
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pwm_getreg(priv, LPC17_40_PWM_MR3_OFFSET));
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}
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else
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#endif
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{
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pwminfo(" DCR: %04x DMAR: %04x\n",
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pwm_getreg(priv, LPC17_40_PWM_MR2_OFFSET),
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pwm_getreg(priv, LPC17_40_PWM_MR3_OFFSET));
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}
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}
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#endif
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/****************************************************************************
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* Name: pwm_timer
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*
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* Description:
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* (Re-)initialize the timer resources and start the pulsed output
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*
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* Input Parameters:
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* priv - A reference to the lower half PWM driver state structure
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* info - A reference to the characteristics of the pulsed output
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure
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*
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****************************************************************************/
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static int pwm_timer(FAR struct lpc17_40_pwmtimer_s *priv,
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FAR const struct pwm_info_s *info)
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{
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irqstate_t flags;
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flags = enter_critical_section();
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putreg32(info->frequency, LPC17_40_PWM1_MR0); /* Set PWMMR0 = number of counts */
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putreg32(info->duty, LPC17_40_PWM1_MR1); /* Set PWM cycle */
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putreg32(LER0_EN | LER3_EN, LPC17_40_PWM1_LER); /* Load Shadow register contents */
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putreg32(PWMENA1, LPC17_40_PWM1_PCR); /* Enable PWM outputs */
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putreg32(TCR_CNT_EN | TCR_PWM_EN, LPC17_40_PWM1_TCR); /* Enable PWM Timer */
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leave_critical_section(flags);
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pwm_dumpregs(priv, "After starting");
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return OK;
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}
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#ifdef XXXXX
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/****************************************************************************
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* Name: pwm_interrupt
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*
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* Description:
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* Handle timer interrupts.
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*
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* Input Parameters:
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* priv - A reference to the lower half PWM driver state structure
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure
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*
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****************************************************************************/
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static int pwm_interrupt(struct lpc17_40_pwmtimer_s *priv)
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{
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uint16_t regval;
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/* Verify that this is an update interrupt. Nothing else is expected. */
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regval = pwm_getreg(priv, STM32_ATIM_SR_OFFSET);
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DEBUGASSERT((regval & ATIM_SR_UIF) != 0);
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/* Clear the UIF interrupt bit */
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pwm_putreg(priv, STM32_ATIM_SR_OFFSET, regval & ~ATIM_SR_UIF);
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/* Calculate the new count by subtracting the number of pulses
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* since the last interrupt.
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*/
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return OK;
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}
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/****************************************************************************
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* Name: pwm_tim1/8interrupt
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*
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* Description:
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* Handle timer 1 and 8 interrupts.
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*
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* Input Parameters:
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* Standard NuttX interrupt inputs
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure
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*
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****************************************************************************/
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static int pwm_tim1interrupt(int irq, void *context, FAR void *arg)
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{
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return pwm_interrupt(&g_pwm1dev);
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}
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/****************************************************************************
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* Name: pwm_set_apb_clock
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*
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* Description:
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* Enable or disable APB clock for the timer peripheral
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*
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* Input Parameters:
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* dev - A reference to the lower half PWM driver state structure
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* on - Enable clock if 'on' is 'true' and disable if 'false'
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*
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****************************************************************************/
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static void pwm_set_apb_clock(FAR struct lpc17_40_pwmtimer_s *priv, bool on)
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{
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uint32_t en_bit;
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uint32_t regaddr;
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/* Determine which timer to configure */
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switch (priv->timid)
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{
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#ifdef CONFIG_LPC17_40_PWM1
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case 1:
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regaddr = STM32_RCC_APB2ENR;
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en_bit = RCC_APB2ENR_TIM1EN;
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break;
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#endif
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}
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/* Enable/disable APB 1/2 clock for timer */
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if (on)
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{
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modifyreg32(regaddr, 0, en_bit);
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}
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else
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{
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modifyreg32(regaddr, en_bit, 0);
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}
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}
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#endif
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/****************************************************************************
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* Name: pwm_setup
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*
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* Description:
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* This method is called when the driver is opened. The lower half driver
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* should configure and initialize the device so that it is ready for use.
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* It should not, however, output pulses until the start method is called.
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*
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* Input Parameters:
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* dev - A reference to the lower half PWM driver state structure
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure
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*
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* Assumptions:
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* APB1 or 2 clocking for the GPIOs has already been configured by the RCC
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* logic at power up.
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*
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****************************************************************************/
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static int pwm_setup(FAR struct pwm_lowerhalf_s *dev)
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{
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FAR struct lpc17_40_pwmtimer_s *priv = (FAR struct lpc17_40_pwmtimer_s *)dev;
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irqstate_t flags;
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uint32_t regval;
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flags = enter_critical_section();
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/* Power on the pwm peripheral */
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regval = getreg32(LPC17_40_SYSCON_PCONP);
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regval |= SYSCON_PCONP_PCPWM1;
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putreg32(regval, LPC17_40_SYSCON_PCONP);
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/* Select clock for the pwm peripheral */
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regval = getreg32(LPC17_40_SYSCON_PCLKSEL0);
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regval &= ~(0x3 << 12); /* PCLK_MC peripheral clk = CCLK = 12.5 MHz */
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regval |= (0x1 << 12); /* PCLK_MC peripheral clk = CCLK = 12.5 MHz */
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putreg32(regval, LPC17_40_SYSCON_PCLKSEL0);
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priv->pclk = (0x1 << 12);
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/* Configure the output pin */
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lpc17_40_configgpio(GPIO_PWM1p1_1);
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putreg32(1, LPC17_40_PWM1_PR); /* Prescaler count frequency: Fpclk/1 */
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putreg32(1 << 1, LPC17_40_PWM1_MCR); /* Reset on match register MR0 */
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leave_critical_section(flags);
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pwm_dumpgpio(priv->pincfg, "PWM setup");
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return OK;
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}
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/****************************************************************************
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* Name: pwm_shutdown
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*
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* Description:
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* This method is called when the driver is closed. The lower half driver
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* stop pulsed output, free any resources, disable the timer hardware, and
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* put the system into the lowest possible power usage state
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*
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* Input Parameters:
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* dev - A reference to the lower half PWM driver state structure
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure
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*
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****************************************************************************/
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static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
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{
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FAR struct lpc17_40_pwmtimer_s *priv = (FAR struct lpc17_40_pwmtimer_s *)dev;
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uint32_t pincfg;
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pwminfo("TIM%d pincfg: %08x\n", priv->timid, priv->pincfg);
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/* Make sure that the output has been stopped */
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return OK;
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}
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/****************************************************************************
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* Name: pwm_start
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*
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* Description:
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* (Re-)initialize the timer resources and start the pulsed output
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*
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* Input Parameters:
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* dev - A reference to the lower half PWM driver state structure
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* info - A reference to the characteristics of the pulsed output
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*
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* Returned Value:
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* Zero on success; a negated errno value on failure
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*
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****************************************************************************/
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static int pwm_start(FAR struct pwm_lowerhalf_s *dev,
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FAR const struct pwm_info_s *info)
|
|
{
|
|
FAR struct lpc17_40_pwmtimer_s *priv = (FAR struct lpc17_40_pwmtimer_s *)dev;
|
|
return pwm_timer(priv, info);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: pwm_stop
|
|
*
|
|
* Description:
|
|
* Stop the pulsed output and reset the timer resources
|
|
*
|
|
* Input Parameters:
|
|
* dev - A reference to the lower half PWM driver state structure
|
|
*
|
|
* Returned Value:
|
|
* Zero on success; a negated errno value on failure
|
|
*
|
|
* Assumptions:
|
|
* This function is called to stop the pulsed output at anytime. This
|
|
* method is also called from the timer interrupt handler when a repetition
|
|
* count expires... automatically stopping the timer.
|
|
*
|
|
****************************************************************************/
|
|
|
|
static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
|
|
{
|
|
FAR struct lpc17_40_pwmtimer_s *priv = (FAR struct lpc17_40_pwmtimer_s *)dev;
|
|
uint32_t resetbit;
|
|
uint32_t regaddr;
|
|
uint32_t regval;
|
|
irqstate_t flags;
|
|
|
|
pwminfo("TIM%d\n", priv->timid);
|
|
|
|
/* Disable interrupts momentary to stop any ongoing timer processing and
|
|
* to prevent any concurrent access to the reset register.
|
|
*/
|
|
|
|
flags = enter_critical_section();
|
|
|
|
/* Disable further interrupts and stop the timer */
|
|
|
|
/* Determine which timer to reset */
|
|
|
|
switch (priv->timid)
|
|
{
|
|
#ifdef CONFIG_LPC17_40_PWM1
|
|
case 1:
|
|
break;
|
|
#endif
|
|
}
|
|
|
|
/* Reset the timer - stopping the output and putting the timer back
|
|
* into a state where pwm_start() can be called.
|
|
*/
|
|
|
|
leave_critical_section(flags);
|
|
|
|
pwminfo("regaddr: %08x resetbit: %08x\n", regaddr, resetbit);
|
|
pwm_dumpregs(priv, "After stop");
|
|
return OK;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: pwm_ioctl
|
|
*
|
|
* Description:
|
|
* Lower-half logic may support platform-specific ioctl commands
|
|
*
|
|
* Input Parameters:
|
|
* dev - A reference to the lower half PWM driver state structure
|
|
* cmd - The ioctl command
|
|
* arg - The argument accompanying the ioctl command
|
|
*
|
|
* Returned Value:
|
|
* Zero on success; a negated errno value on failure
|
|
*
|
|
****************************************************************************/
|
|
|
|
static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg)
|
|
{
|
|
#ifdef CONFIG_DEBUG_PWM_INFO
|
|
FAR struct lpc17_40_pwmtimer_s *priv = (FAR struct lpc17_40_pwmtimer_s *)dev;
|
|
|
|
/* There are no platform-specific ioctl commands */
|
|
|
|
pwminfo("TIM%d\n", priv->timid);
|
|
#endif
|
|
return -ENOTTY;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Public Functions
|
|
****************************************************************************/
|
|
|
|
/****************************************************************************
|
|
* Name: lpc17_40_pwminitialize
|
|
*
|
|
* Description:
|
|
* Initialize one timer for use with the upper_level PWM driver.
|
|
*
|
|
* Input Parameters:
|
|
* timer - A number identifying the timer use. The number of valid timer
|
|
* IDs varies with the STM32 MCU and MCU family but is somewhere in
|
|
* the range of {1,..,14}.
|
|
*
|
|
* Returned Value:
|
|
* On success, a pointer to the STM32 lower half PWM driver is returned.
|
|
* NULL is returned on any failure.
|
|
*
|
|
****************************************************************************/
|
|
|
|
FAR struct pwm_lowerhalf_s *lpc17_40_pwminitialize(int timer)
|
|
{
|
|
FAR struct lpc17_40_pwmtimer_s *lower;
|
|
|
|
pwminfo("TIM%d\n", timer);
|
|
|
|
switch (timer)
|
|
{
|
|
#ifdef CONFIG_LPC17_40_PWM1
|
|
case 0:
|
|
lower = &g_pwm1dev;
|
|
|
|
/* Attach but disable the TIM1 update interrupt */
|
|
|
|
break;
|
|
#endif
|
|
|
|
default:
|
|
pwmerr("ERROR: No such timer configured\n");
|
|
return NULL;
|
|
}
|
|
|
|
return (FAR struct pwm_lowerhalf_s *)lower;
|
|
}
|
|
|
|
#endif /* CONFIG_LPC17_40_TIMn_PWM, n = 1,...,14 */
|