e72dce9e1b
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1951 42af7a65-404d-4744-a932-0658087f49c3
246 lines
9.4 KiB
C
246 lines
9.4 KiB
C
/****************************************************************************
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* arch/z16f/irq.h
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* arch/chip/irq.h
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*
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* Copyright (C) 2008 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/* This file should never be included directed but, rather,
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* only indirectly through nuttx/irq.h (via arch/irq.h)
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*/
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#ifndef __ARCH_Z16F_IRQ_H
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#define __ARCH_Z16F_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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/****************************************************************************
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* Definitions
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****************************************************************************/
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/* Interrupt Vectors (excluding reset and sysexec which are handled differently) */
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#define Z16F_IRQ_IRQ0 ( 0) /* First of 8 IRQs controlled by IRQ0 registers */
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#define Z16F_IRQ_ADC ( 0) /* Vector: 0x2C IRQ0.0 ADC */
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#define Z16F_IRQ_SPI ( 1) /* Vector: 0x28 IRQ0.1 SPI */
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#define Z16F_IRQ_I2C ( 2) /* Vector: 0x24 IRQ0.2 I2C */
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#define Z16F_IRQ_UART0TX ( 3) /* Vector: 0x20 IRQ0.3 UART0 TX */
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#define Z16F_IRQ_UART0RX ( 4) /* Vector: 0x1C IRQ0.4 UART0 RX */
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#define Z16F_IRQ_TIMER0 ( 5) /* Vector: 0x18 IRQ0.5 Timer 0 */
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#define Z16F_IRQ_TIMER1 ( 6) /* Vector: 0x14 IRQ0.6 Timer 1 */
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#define Z16F_IRQ_TIMER2 ( 7) /* Vector: 0x10 IRQ0.7 Timer 2 */
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#define Z16F_IRQ_IRQ1 ( 8) /* First of 8 IRQs controlled by IRQ1 registers */
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#define Z16F_IRQ_P0AD ( 8) /* Vector: 0x4C IRQ1.0 Port A/D0, rising/falling edge */
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#define Z16F_IRQ_P1AD ( 9) /* Vector: 0x48 IRQ1.1 Port A/D1, rising/falling edge */
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#define Z16F_IRQ_P2AD (10) /* Vector: 0x44 IRQ1.2 Port A/D2, rising/falling edge */
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#define Z16F_IRQ_P3AD (11) /* Vector: 0x40 IRQ1.3 Port A/D3, rising/falling edge */
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#define Z16F_IRQ_P4AD (12) /* Vector: 0x3C IRQ1.4 Port A/D4, rising/falling edge */
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#define Z16F_IRQ_P5AD (13) /* Vector: 0x38 IRQ1.5 Port A/D5, rising/falling edge */
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#define Z16F_IRQ_P6AD (14) /* Vector: 0x34 IRQ1.6 Port A/D6, rising/falling edge */
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#define Z16F_IRQ_P7AD (15) /* Vector: 0x30 IRQ1.7 Port A/D7, rising/falling edge */
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#define Z16F_IRQ_IRQ2 (16) /* First of 8 IRQs controlled by IRQ2 registers */
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#define Z16F_IRQ_C0 (16) /* Vector: IRQ2.0 0x6C Port C0, both edges DMA0 */
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#define Z16F_IRQ_C1 (17) /* Vector: IRQ2.1 0x68 Port C1, both edges DMA1 */
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#define Z16F_IRQ_C2 (18) /* Vector: IRQ2.2 0x64 Port C2, both edges DMA2 */
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#define Z16F_IRQ_C3 (19) /* Vector: IRQ2.3 0x60 Port C3, both edges DMA3 */
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#define Z16F_IRQ_PWMFAULT (20) /* Vector: IRQ2.4 0x5C PWM Fault */
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#define Z16F_IRQ_UART1TX (21) /* Vector: IRQ2.5 0x58 UART1 TX */
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#define Z16F_IRQ_UART1RX (22) /* Vector: IRQ2.6 0x54 UART1 RX */
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#define Z16F_IRQ_PWMTIMER (23) /* Vector: IRQ2.7 0x50 PWM Timer */
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#define Z16F_IRQ_SYSTIMER Z16F_IRQ_TIMER0
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#define NR_IRQS (24)
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/* These macros will map an IRQ to a register bit position */
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#define Z16F_IRQ0_BIT(i) (1 << ((i)-Z16F_IRQ_IRQ0))
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#define Z16F_IRQ1_BIT(i) (1 << ((i)-Z16F_IRQ_IRQ1))
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#define Z16F_IRQ2_BIT(i) (1 << ((i)-Z16F_IRQ_IRQ2))
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/* IRQ Stack Frame Format
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*
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* This stack frame is created on each interrupt. These registers are stored
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* in the TCB to many context switches.
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*
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* The following represent all of the "static" registers r8-r15. These
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* are registers that whose value must be retained across function calls.
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* These registers must be saved bothby interrupt handling context switch
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* switch logic and also by user-initiated context switches.
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*
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* Registers are saved in the order consistent with pushmho <r8-r15>,
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* that is with r15 pushed first and r8 push last. Since the z16f has
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* a "push-down" stack, the registers will be "in order" in memory.
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*/
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#define REG_R8 ( 0) /* 32-bits: R8 */
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#define REG_R9 ( 2) /* 32-bits: R9 */
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#define REG_R10 ( 4) /* 32-bits: R10 */
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#define REG_R11 ( 6) /* 32-bits: R11 */
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#define REG_R12 ( 8) /* 32-bits: R12 */
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#define REG_R13 (10) /* 32-bits: R13 */
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/* The frame pointer and the SP at the point of task resumption must
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* always be saved.
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*/
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#define REG_R14 (12) /* 32-bits: R14 = fp */
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#define REG_FP REG_R14
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#define REG_R15 (14) /* 32-bits: R15 = sp */
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#define REG_SP REG_R15
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/* The following represent all of the "volatile" registers r0-r7. These
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* are registers that whose value need not be retained across function
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* calls. These registers must be saved by interrupt handling context
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* switch logic but not by user-initiated context switches.
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*
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* Registers are saved in the order consistent with pushmlo <r0-r7>,
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* that is with r7 pushed first and r0 push last. Since the z16f has
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* a "push-down" stack, the registers will be "in order" in memory.
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*/
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#define REG_R0 (16) /* 32-bits: R0 */
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#define REG_R1 (18) /* 32-bits: R1 */
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#define REG_R2 (20) /* 32-bits: R2 */
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#define REG_R3 (22) /* 32-bits: R3 */
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#define REG_R4 (24) /* 32-bits: R4 */
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#define REG_R5 (26) /* 32-bits: R5 */
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#define REG_R6 (28) /* 32-bits: R6 */
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#define REG_R7 (30) /* 32-bits: R7 */
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/* The following two offsets represent the state of the stack on entry
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* into the interrupt handler:
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*
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* TOS[0] = PC[31:24]
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* TOS[1] = PC[23:16]
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* TOS[2] = PC[15:8]
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* TOS[3] = PC[7:0]
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* TOS[4] = 0
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* TOS[5] = flags
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*/
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#define REG_PC (32) /* 32-bits: Return PC */
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#define REG_FLAGS (34) /* 16-bits: Flags register (with 0x00 padding) */
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#define XCPTCONTEXT_REGS (35)
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#define XCPTCONTEXT_SIZE (2 * XCPTCONTEXT_REGS)
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/* This is the type of the register save array */
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typedef uint16 chipreg_t;
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/* This struct defines the way the registers are stored. */
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struct xcptcontext
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{
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/* Register save area */
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uint16 regs[XCPTCONTEXT_REGS];
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/* The following function pointer is non-zero if there
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* are pending signals to be processed.
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*/
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#ifndef CONFIG_DISABLE_SIGNALS
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CODE void *sigdeliver; /* Actual type is sig_deliver_t */
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/* The following retains that state during signal execution */
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uint32 saved_pc; /* Saved return address */
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uint16 saved_i; /* Saved interrupt state */
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#endif
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};
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#endif
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/* The ZDS-II provides built-in operations to test & disable and to restore
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* the interrupt state.
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*
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* irqstate_t irqsave(void);
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* void irqrestore(irqstate_t flags);
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*/
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#ifdef __ZILOG__
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# define irqsave() TDI()
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# define irqrestore(f) RI(f)
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#endif
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/****************************************************************************
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* Inline functions
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****************************************************************************/
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/****************************************************************************
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* Public Variables
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C" {
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#else
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#define EXTERN extern
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#endif
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/* ZDS-II intrinsic functions (normally declared in zneo.h) */
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EXTERN intrinsic void EI(void);
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EXTERN intrinsic void DI(void);
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EXTERN intrinsic void RI(unsigned short);
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EXTERN intrinsic SET_VECTOR(int,void (* func) (void));
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EXTERN intrinsic unsigned short TDI(void);
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#ifndef __ZILOG__
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EXTERN irqstate_t irqsave(void);
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EXTERN void irqrestore(irqstate_t flags);
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif /* __ARCH_Z16F_IRQ_H */
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