279 lines
8.0 KiB
C
279 lines
8.0 KiB
C
/****************************************************************************
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* arch/arm/src/s32k3xx/s32k3xx_start.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* Copyright 2022 NXP */
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <assert.h>
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#include <debug.h>
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#include <nuttx/cache.h>
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#include <nuttx/init.h>
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#include <arch/board/board.h>
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#include <arch/irq.h>
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#include "arm_internal.h"
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#include "nvic.h"
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#ifdef CONFIG_BUILD_PROTECTED
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# include "s32k3xx_userspace.h"
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#endif
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#include "hardware/s32k3xx_mcm.h"
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#include "hardware/s32k3xx_mc_me.h"
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#include "s32k3xx_clockconfig.h"
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#include "s32k3xx_lowputc.h"
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#include "s32k3xx_serial.h"
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#include "s32k3xx_swt.h"
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#include "s32k3xx_start.h"
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#if defined(CONFIG_ARCH_USE_MPU)
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#include "s32k3xx_mpuinit.h"
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#endif
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#ifdef CONFIG_S32K3XX_PROGMEM
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#include "s32k3xx_progmem.h"
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#endif
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#ifdef CONFIG_S32K3XX_EEEPROM
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#include "s32k3xx_eeeprom.h"
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Memory Map ***************************************************************/
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/* 0x0040:1000 - Beginning of the internal FLASH. Address of vectors.
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* Mapped as boot memory address CM7_0_START_ADDRESS at reset.
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* 0x007d:0fff - End of flash region (assuming the max of 2MiB of FLASH).
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* 0x2040:8000 - Start of internal SRAM and start of .data (_sdata)
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*
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* The on-chip RAM is split in two regions: SRAM_L and SRAM_U.
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* The RAM is implemented such that the SRAM_L and SRAM_U
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* ranges form a contiguous block in the memory map. Thus, the
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* actual SRAM start address is SAM_L which some MCU-specific
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* value in the range 0x1000:0000 and 0x1fff:ffff. SRAM_U
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* then always starts at 0x2000:0000
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* - End of .data (_edata) and start of .bss (_sbss)
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* - End of .bss (_ebss) and bottom of idle stack
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* - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack,
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* start of heap. NOTE that the ARM uses a decrement before
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* store stack so that the correct initial value is the end of
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* the stack + 4;
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* 0x2044:4000 - End of internal SRAM and end of heap. The actual end of
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* SRAM_U will depend on the amount of memory supported by the
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* MCU/
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*
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* NOTE: ARM EABI requires 64 bit stack alignment.
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*/
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#define STARTUP_ECC_INITVALUE 0
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/****************************************************************************
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* Name: showprogress
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*
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* Description:
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* Print a character on the UART to show boot status.
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*
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****************************************************************************/
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#ifdef CONFIG_DEBUG_FEATURES
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# define showprogress(c) s32k3xx_lowputc(c)
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#else
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# define showprogress(c)
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#endif
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/****************************************************************************
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* Private Types
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****************************************************************************/
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extern uint8_t SRAM_BASE_ADDR[];
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extern uint8_t SRAM_INIT_END_ADDR[];
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extern uint8_t ITCM_BASE_ADDR[];
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extern uint8_t ITCM_END_ADDR[];
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extern uint8_t DTCM_BASE_ADDR[];
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extern uint8_t DTCM_END_ADDR[];
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extern uint8_t FLASH_BASE_ADDR[];
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extern uint8_t FLASH_END_ADDR[];
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: __start
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*
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* Description:
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* This is the reset entry point.
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*
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****************************************************************************/
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void s32k3xx_start(void)
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{
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register uint64_t *src;
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register uint64_t *dest;
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/* Technically startup.S did initialize SRAM
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* but if don't set init value here again
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* then on a cold boot we go into a bootloop somehow
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*/
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dest = (uint64_t *)SRAM_BASE_ADDR;
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while (dest < (uint64_t *)SRAM_INIT_END_ADDR)
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{
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*dest++ = STARTUP_ECC_INITVALUE;
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}
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/* ITCM */
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dest = (uint64_t *)ITCM_BASE_ADDR;
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while (dest < (uint64_t *)ITCM_END_ADDR)
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{
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*dest++ = STARTUP_ECC_INITVALUE;
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}
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/* DTCM */
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dest = (uint64_t *)DTCM_BASE_ADDR;
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while (dest < (uint64_t *)DTCM_END_ADDR)
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{
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*dest++ = STARTUP_ECC_INITVALUE;
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}
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/* Clear .bss. We'll do this inline (vs. calling memset) just to be
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* certain that there are no issues with the state of global variables.
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*/
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for (dest = (uint64_t *)_sbss; dest < (uint64_t *)_ebss; )
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{
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*dest++ = 0;
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}
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#ifdef CONFIG_BOOT_RUNFROMFLASH
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/* Move the initialized data section from his temporary holding spot in
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* FLASH into the correct place in SRAM. The correct place in SRAM is
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* give by _sdata and _edata. The temporary location is in FLASH at the
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* end of all of the other read-only data (.text, .rodata) at _eronly.
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*/
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for (src = (uint64_t *)_eronly, dest = (uint64_t *)_sdata;
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dest < (uint64_t *)_edata;
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)
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{
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*dest++ = *src++;
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}
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#endif
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/* Copy any necessary code sections from FLASH to RAM. The correct
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* destination in SRAM is given by _sramfuncs and _eramfuncs. The
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* temporary location is in flash after the data initialization code
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* at _framfuncs. This should be done before s32k3xx_clockconfig() is
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* called (in case it has some dependency on initialized C variables).
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*/
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#ifdef CONFIG_ARCH_RAMFUNCS
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for (src = (uint64_t *)_framfuncs, dest = (uint64_t *)_sramfuncs;
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dest < (uint64_t *)_eramfuncs;
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)
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{
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*dest++ = *src++;
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}
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#endif
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/* Configure the clocking and the console uart so that we can get debug
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* output as soon as possible. NOTE: That this logic must not assume that
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* .bss or .data have been initialized.
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*/
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DEBUGVERIFY(s32k3xx_clockconfig(&g_initial_clkconfig));
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s32k3xx_lowsetup();
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showprogress('B');
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/* Initialize the FPU (if configured) */
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arm_fpuconfig();
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#ifdef CONFIG_ARM_MPU
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#ifdef CONFIG_BUILD_PROTECTED
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/* For the case of the separate user-/kernel-space build, perform whatever
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* platform specific initialization of the user memory is required.
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* Normally this just means initializing the user space .data and .bss
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* segments.
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*/
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s32k3xx_userspace();
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#endif
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/* Configure the MPU to permit user-space access to its FLASH and RAM (for
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* CONFIG_BUILD_PROTECTED) or to manage cache properties in external
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* memory regions.
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*/
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s32k3xx_mpuinitialize();
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showprogress('D');
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#endif
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/* Enable I- and D-Caches */
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up_enable_icache();
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up_enable_dcache();
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showprogress('C');
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/* Perform early serial initialization */
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#ifdef USE_EARLYSERIALINIT
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s32k3xx_earlyserialinit();
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#endif
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showprogress('E');
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#ifdef CONFIG_S32K3XX_PROGMEM
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s32k3xx_progmem_init();
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#endif
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#ifdef CONFIG_S32K3XX_EEEPROM
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s32k3xx_eeeprom_init();
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#endif
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/* Initialize on-board resources */
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showprogress('G');
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s32k3xx_board_initialize();
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/* Then start NuttX */
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showprogress('\r');
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showprogress('\n');
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nx_start();
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/* Shouldn't get here */
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for (; ; );
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}
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