627 lines
20 KiB
C
627 lines
20 KiB
C
/****************************************************************************
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* arch/arm/src/stm32l4/stm32l4_adc.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_ADC_H
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#define __ARCH_ARM_SRC_STM32L4_STM32L4_ADC_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/analog/adc.h>
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#include "chip.h"
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#include "hardware/stm32l4_adc.h"
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#include "stm32l4_dma.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Configuration ************************************************************/
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/* Timer devices may be used for different purposes. One special purpose is
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* to control periodic ADC sampling. If CONFIG_STM32L4_TIMn is defined then
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* CONFIG_STM32L4_TIMn_ADC must also be defined to indicate that timer "n" is
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* intended to be used for that purpose. Timers 1,2,3,6 and 15 may be used on
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* STM32L4X3, while STM32L4X6 adds support for timers 4 and 8 as well.
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*/
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#ifndef CONFIG_STM32L4_TIM1
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# undef CONFIG_STM32L4_TIM1_ADC
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# undef CONFIG_STM32L4_TIM1_ADC1
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# undef CONFIG_STM32L4_TIM1_ADC2
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# undef CONFIG_STM32L4_TIM1_ADC3
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#endif
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#ifndef CONFIG_STM32L4_TIM2
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# undef CONFIG_STM32L4_TIM2_ADC
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# undef CONFIG_STM32L4_TIM2_ADC1
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# undef CONFIG_STM32L4_TIM2_ADC2
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# undef CONFIG_STM32L4_TIM2_ADC3
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#endif
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#ifndef CONFIG_STM32L4_TIM3
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# undef CONFIG_STM32L4_TIM3_ADC
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# undef CONFIG_STM32L4_TIM3_ADC1
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# undef CONFIG_STM32L4_TIM3_ADC2
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# undef CONFIG_STM32L4_TIM3_ADC3
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#endif
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#ifndef CONFIG_STM32L4_TIM4
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# undef CONFIG_STM32L4_TIM4_ADC
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# undef CONFIG_STM32L4_TIM4_ADC1
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# undef CONFIG_STM32L4_TIM4_ADC2
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# undef CONFIG_STM32L4_TIM4_ADC3
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#endif
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#ifndef CONFIG_STM32L4_TIM6
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# undef CONFIG_STM32L4_TIM6_ADC
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# undef CONFIG_STM32L4_TIM6_ADC1
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# undef CONFIG_STM32L4_TIM6_ADC2
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# undef CONFIG_STM32L4_TIM6_ADC3
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#endif
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#ifndef CONFIG_STM32L4_TIM8
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# undef CONFIG_STM32L4_TIM8_ADC
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# undef CONFIG_STM32L4_TIM8_ADC1
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# undef CONFIG_STM32L4_TIM8_ADC2
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# undef CONFIG_STM32L4_TIM8_ADC3
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#endif
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#ifndef CONFIG_STM32L4_TIM15
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# undef CONFIG_STM32L4_TIM15_ADC
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# undef CONFIG_STM32L4_TIM15_ADC1
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# undef CONFIG_STM32L4_TIM15_ADC2
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# undef CONFIG_STM32L4_TIM15_ADC3
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#endif
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/* Up to 3 ADC interfaces are supported */
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#if STM32L4_NADC < 3
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# undef CONFIG_STM32L4_ADC3
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#endif
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#if STM32L4_NADC < 2
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# undef CONFIG_STM32L4_ADC2
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#endif
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#if STM32L4_NADC < 1
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# undef CONFIG_STM32L4_ADC1
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#endif
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#if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) || \
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defined(CONFIG_STM32L4_ADC3)
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/* ADC output to DFSDM support. Note that DFSDM and DMA are
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* mutually exclusive.
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*/
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#undef ADC_HAVE_DFSDM
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#if defined(CONFIG_STM32L4_ADC1_OUTPUT_DFSDM) || \
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defined(CONFIG_STM32L4_ADC2_OUTPUT_DFSDM) || \
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defined(CONFIG_STM32L4_ADC3_OUTPUT_DFSDM)
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# define ADC_HAVE_DFSDM
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#endif
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#if defined(CONFIG_STM32L4_ADC1_OUTPUT_DFSDM)
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# define ADC1_HAVE_DFSDM 1
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# undef CONFIG_STM32L4_ADC1_DMA
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#else
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# undef ADC1_HAVE_DFSDM
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#endif
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#if defined(CONFIG_STM32L4_ADC2_OUTPUT_DFSDM)
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# define ADC2_HAVE_DFSDM 1
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# undef CONFIG_STM32L4_ADC2_DMA
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#else
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# undef ADC2_HAVE_DFSDM
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#endif
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#if defined(CONFIG_STM32L4_ADC3_OUTPUT_DFSDM)
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# define ADC3_HAVE_DFSDM 1
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# undef CONFIG_STM32L4_ADC3_DMA
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#else
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# undef ADC3_HAVE_DFSDM
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#endif
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/* DMA support */
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#undef ADC_HAVE_DMA
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#if defined(CONFIG_STM32L4_ADC1_DMA) || defined(CONFIG_STM32L4_ADC2_DMA) || \
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defined(CONFIG_STM32L4_ADC3_DMA)
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# define ADC_HAVE_DMA 1
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#endif
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#ifdef CONFIG_STM32L4_ADC1_DMA
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# define ADC1_HAVE_DMA 1
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#else
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# undef ADC1_HAVE_DMA
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#endif
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#ifdef CONFIG_STM32L4_ADC2_DMA
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# define ADC2_HAVE_DMA 1
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#else
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# undef ADC2_HAVE_DMA
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#endif
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#ifdef CONFIG_STM32L4_ADC3_DMA
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# define ADC3_HAVE_DMA 1
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#else
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# undef ADC3_HAVE_DMA
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#endif
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/* Injected channels support */
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#if (defined(CONFIG_STM32L4_ADC1) && (CONFIG_STM32L4_ADC1_INJ_CHAN > 0)) || \
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(defined(CONFIG_STM32L4_ADC2) && (CONFIG_STM32L4_ADC2_INJ_CHAN > 0)) || \
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(defined(CONFIG_STM32L4_ADC3) && (CONFIG_STM32L4_ADC3_INJ_CHAN > 0))
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# define ADC_HAVE_INJECTED
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#endif
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/* Timer configuration: If a timer trigger is specified, then get
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* information about the timer.
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*/
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#if defined(CONFIG_STM32L4_TIM1_ADC1)
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# define ADC1_HAVE_TIMER 1
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# define ADC1_TIMER_BASE STM32L4_TIM1_BASE
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# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM1_CLKIN
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# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM1_ADC_CHAN
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#elif defined(CONFIG_STM32L4_TIM2_ADC1)
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# define ADC1_HAVE_TIMER 1
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# define ADC1_TIMER_BASE STM32L4_TIM2_BASE
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# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM2_CLKIN
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# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM2_ADC_CHAN
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#elif defined(CONFIG_STM32L4_TIM3_ADC1)
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# define ADC1_HAVE_TIMER 1
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# define ADC1_TIMER_BASE STM32L4_TIM3_BASE
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# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM3_CLKIN
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# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM3_ADC_CHAN
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#elif defined(CONFIG_STM32L4_TIM4_ADC1)
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# define ADC1_HAVE_TIMER 1
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# define ADC1_TIMER_BASE STM32L4_TIM4_BASE
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# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM4_CLKIN
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# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM4_ADC_CHAN
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#elif defined(CONFIG_STM32L4_TIM6_ADC1)
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# define ADC1_HAVE_TIMER 1
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# define ADC1_TIMER_BASE STM32L4_TIM6_BASE
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# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM6_CLKIN
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# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM6_ADC_CHAN
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#elif defined(CONFIG_STM32L4_TIM8_ADC1)
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# define ADC1_HAVE_TIMER 1
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# define ADC1_TIMER_BASE STM32L4_TIM8_BASE
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# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM8_CLKIN
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# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM8_ADC_CHAN
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#elif defined(CONFIG_STM32L4_TIM15_ADC1)
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# define ADC1_HAVE_TIMER 1
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# define ADC1_TIMER_BASE STM32L4_TIM15_BASE
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# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM15_CLKIN
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# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM15_ADC_CHAN
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#else
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# undef ADC1_HAVE_TIMER
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#endif
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#ifdef ADC1_HAVE_TIMER
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# ifndef CONFIG_STM32L4_ADC1_SAMPLE_FREQUENCY
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# error "CONFIG_STM32L4_ADC1_SAMPLE_FREQUENCY not defined"
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# endif
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# if ((CONFIG_STM32L4_ADC1_EXTTRIG == 0) && \
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(CONFIG_STM32L4_ADC1_JEXTTRIG == 0))
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# error "ADC1 External trigger must be enabled"
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# endif
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#endif
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#if defined(CONFIG_STM32L4_TIM1_ADC2)
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# define ADC2_HAVE_TIMER 1
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# define ADC2_TIMER_BASE STM32L4_TIM1_BASE
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# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM1_CLKIN
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# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM1_ADC_CHAN
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#elif defined(CONFIG_STM32L4_TIM2_ADC2)
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# define ADC2_HAVE_TIMER 1
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# define ADC2_TIMER_BASE STM32L4_TIM2_BASE
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# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM2_CLKIN
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# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM2_ADC_CHAN
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#elif defined(CONFIG_STM32L4_TIM3_ADC2)
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# define ADC2_HAVE_TIMER 1
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# define ADC2_TIMER_BASE STM32L4_TIM3_BASE
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# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM3_CLKIN
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# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM3_ADC_CHAN
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#elif defined(CONFIG_STM32L4_TIM4_ADC2)
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# define ADC2_HAVE_TIMER 1
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# define ADC2_TIMER_BASE STM32L4_TIM4_BASE
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# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM4_CLKIN
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# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM4_ADC_CHAN
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#elif defined(CONFIG_STM32L4_TIM6_ADC2)
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# define ADC2_HAVE_TIMER 1
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# define ADC2_TIMER_BASE STM32L4_TIM6_BASE
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# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM6_CLKIN
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# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM6_ADC_CHAN
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#elif defined(CONFIG_STM32L4_TIM8_ADC2)
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# define ADC2_HAVE_TIMER 1
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# define ADC2_TIMER_BASE STM32L4_TIM8_BASE
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# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM8_CLKIN
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# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM8_ADC_CHAN
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#elif defined(CONFIG_STM32L4_TIM15_ADC2)
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# define ADC2_HAVE_TIMER 1
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# define ADC2_TIMER_BASE STM32L4_TIM15_BASE
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# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM15_CLKIN
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# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM15_ADC_CHAN
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#else
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# undef ADC2_HAVE_TIMER
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#endif
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#ifdef ADC2_HAVE_TIMER
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# ifndef CONFIG_STM32L4_ADC2_SAMPLE_FREQUENCY
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# error "CONFIG_STM32L4_ADC2_SAMPLE_FREQUENCY not defined"
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# endif
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# if ((CONFIG_STM32L4_ADC2_EXTTRIG == 0) && \
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(CONFIG_STM32L4_ADC2_JEXTTRIG == 0))
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# error "ADC2 External trigger must be enabled"
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# endif
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#endif
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#if defined(CONFIG_STM32L4_TIM1_ADC3)
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# define ADC3_HAVE_TIMER 1
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# define ADC3_TIMER_BASE STM32L4_TIM1_BASE
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# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM1_CLKIN
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# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM1_ADC_CHAN
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#elif defined(CONFIG_STM32L4_TIM2_ADC3)
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# define ADC3_HAVE_TIMER 1
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# define ADC3_TIMER_BASE STM32L4_TIM2_BASE
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# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM2_CLKIN
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# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM1_ADC_CHAN
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#elif defined(CONFIG_STM32L4_TIM3_ADC3)
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# define ADC3_HAVE_TIMER 1
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# define ADC3_TIMER_BASE STM32L4_TIM3_BASE
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# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM3_CLKIN
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# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM3_ADC_CHAN
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#elif defined(CONFIG_STM32L4_TIM4_ADC3)
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# define ADC3_HAVE_TIMER 1
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# define ADC3_TIMER_BASE STM32L4_TIM4_BASE
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# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM4_CLKIN
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# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM4_ADC_CHAN
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#elif defined(CONFIG_STM32L4_TIM6_ADC3)
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# define ADC3_HAVE_TIMER 1
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# define ADC3_TIMER_BASE STM32L4_TIM6_BASE
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# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM6_CLKIN
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# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM6_ADC_CHAN
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#elif defined(CONFIG_STM32L4_TIM8_ADC3)
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# define ADC3_HAVE_TIMER 1
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# define ADC3_TIMER_BASE STM32L4_TIM8_BASE
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# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM8_CLKIN
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# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM8_ADC_CHAN
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#elif defined(CONFIG_STM32L4_TIM15_ADC3)
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# define ADC3_HAVE_TIMER 1
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# define ADC3_TIMER_BASE STM32L4_TIM15_BASE
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# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM15_CLKIN
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# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM15_ADC_CHAN
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#else
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# undef ADC3_HAVE_TIMER
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#endif
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#ifdef ADC3_HAVE_TIMER
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# ifndef CONFIG_STM32L4_ADC3_SAMPLE_FREQUENCY
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# error "CONFIG_STM32L4_ADC3_SAMPLE_FREQUENCY not defined"
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# endif
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# if ((CONFIG_STM32L4_ADC3_EXTTRIG == 0) && \
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(CONFIG_STM32L4_ADC3_JEXTTRIG == 0))
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# error "ADC3 External trigger must be enabled"
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# endif
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#endif
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#if defined(ADC1_HAVE_TIMER) || defined(ADC2_HAVE_TIMER) || \
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defined(ADC3_HAVE_TIMER)
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# define ADC_HAVE_TIMER 1
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#else
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# undef ADC_HAVE_TIMER
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#endif
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/* EXTSEL configuration *****************************************************/
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/* If external trigger is enabled, (CONFIG_STM32L4_ADC1_EXTTRIG > 0),
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* ADCx_EXTSEL_VALUE is set based on trigger polarity and event number. No
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* effort is made to check if the configuration is valid.
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*/
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#ifdef CONFIG_STM32L4_ADC1_EXTTRIG
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# if CONFIG_STM32L4_ADC1_EXTTRIG > 0
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# define ADC1_EXTCFG_VALUE \
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ADC_CFGR_EXTEN(CONFIG_STM32L4_ADC1_EXTTRIG) | \
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ADC_CFGR_EXTSEL(CONFIG_STM32L4_ADC1_EXTSEL)
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# endif
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#endif /* CONFIG_STM32L4_ADC1_EXTTRIG */
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#ifdef ADC1_EXTCFG_VALUE
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# define ADC1_HAVE_EXTCFG 1
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#else
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# undef ADC1_HAVE_EXTCFG
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#endif
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#ifdef CONFIG_STM32L4_ADC2_EXTTRIG
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# if CONFIG_STM32L4_ADC2_EXTTRIG > 0
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# define ADC2_EXTCFG_VALUE \
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ADC_CFGR_EXTEN(CONFIG_STM32L4_ADC2_EXTTRIG) | \
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ADC_CFGR_EXTSEL(CONFIG_STM32L4_ADC2_EXTSEL)
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# endif
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#endif /* CONFIG_STM32L4_ADC2_EXTTRIG */
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#ifdef ADC2_EXTCFG_VALUE
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# define ADC2_HAVE_EXTCFG 1
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#else
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# undef ADC2_HAVE_EXTCFG
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#endif
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#ifdef CONFIG_STM32L4_ADC3_EXTTRIG
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# if CONFIG_STM32L4_ADC3_EXTTRIG > 0
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# define ADC3_EXTCFG_VALUE \
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ADC_CFGR_EXTEN(CONFIG_STM32L4_ADC3_EXTTRIG) | \
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ADC_CFGR_EXTSEL(CONFIG_STM32L4_ADC3_EXTSEL)
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# endif
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#endif /* CONFIG_STM32L4_ADC3_EXTTRIG */
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#ifdef ADC3_EXTCFG_VALUE
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# define ADC3_HAVE_EXTCFG 1
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#else
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# undef ADC3_HAVE_EXTCFG
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#endif
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#if defined(ADC1_HAVE_EXTCFG) || defined(ADC2_HAVE_EXTCFG) || \
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defined(ADC3_HAVE_EXTCFG)
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# define ADC_HAVE_EXTCFG
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#endif
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/* JEXTSEL configuration ****************************************************/
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#ifdef CONFIG_STM32L4_ADC1_JEXTTRIG
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# if CONFIG_STM32L4_ADC1_JEXTTRIG > 0
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# define ADC1_JEXTCFG_VALUE \
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ADC_JSQR_JEXTEN(CONFIG_STM32L4_ADC1_JEXTTRIG) | \
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ADC_JSQR_JEXTSEL(CONFIG_STM32L4_ADC1_JEXTSEL)
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# endif
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#endif /* CONFIG_STM32L4_ADC1_JEXTTRIG */
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#ifdef ADC1_JEXTCFG_VALUE
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# define ADC1_HAVE_JEXTCFG 1
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#endif
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#ifdef CONFIG_STM32L4_ADC2_JEXTTRIG
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# if CONFIG_STM32L4_ADC2_JEXTTRIG > 0
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# define ADC2_JEXTCFG_VALUE \
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ADC_JSQR_JEXTEN(CONFIG_STM32L4_ADC2_JEXTTRIG) | \
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ADC_JSQR_JEXTSEL(CONFIG_STM32L4_ADC2_JEXTSEL)
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# endif
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#endif /* CONFIG_STM32L4_ADC2_JEXTTRIG */
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#ifdef ADC2_JEXTCFG_VALUE
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# define ADC2_HAVE_JEXTCFG 1
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#endif
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#ifdef CONFIG_STM32L4_ADC3_JEXTTRIG
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# if CONFIG_STM32L4_ADC3_JEXTTRIG > 0
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# define ADC3_JEXTCFG_VALUE \
|
|
ADC_JSQR_JEXTEN(CONFIG_STM32L4_ADC3_JEXTTRIG) | \
|
|
ADC_JSQR_JEXTSEL(CONFIG_STM32L4_ADC3_JEXTSEL)
|
|
# endif
|
|
#endif /* CONFIG_STM32L4_ADC3_JEXTTRIG */
|
|
|
|
#ifdef ADC3_JEXTCFG_VALUE
|
|
# define ADC3_HAVE_JEXTCFG 1
|
|
#endif
|
|
|
|
#if defined(ADC1_HAVE_JEXTCFG) || defined(ADC2_HAVE_JEXTCFG) || \
|
|
defined(ADC3_HAVE_JEXTCFG)
|
|
# define ADC_HAVE_JEXTCFG
|
|
#endif
|
|
|
|
/* ADC interrupts ***********************************************************/
|
|
|
|
#define ADC_ISR_EOC ADC_INT_EOC
|
|
#define ADC_IER_EOC ADC_INT_EOC
|
|
#define ADC_ISR_EOS ADC_INT_EOS
|
|
#define ADC_IER_EOS ADC_INT_EOS
|
|
#define ADC_ISR_AWD ADC_INT_AWD1
|
|
#define ADC_IER_AWD ADC_INT_AWD1
|
|
#define ADC_ISR_JEOC ADC_INT_JEOC
|
|
#define ADC_IER_JEOC ADC_INT_JEOC
|
|
#define ADC_ISR_OVR ADC_INT_OVR
|
|
#define ADC_IER_OVR ADC_INT_OVR
|
|
#define ADC_ISR_JEOS ADC_INT_JEOS
|
|
#define ADC_IER_JEOS ADC_INT_JEOS
|
|
|
|
#define ADC_ISR_ALLINTS (ADC_ISR_EOC | ADC_ISR_EOS | ADC_ISR_AWD | \
|
|
ADC_ISR_JEOC | ADC_ISR_JEOS | ADC_ISR_OVR)
|
|
#define ADC_IER_ALLINTS (ADC_IER_EOC | ADC_IER_EOS | ADC_IER_AWD | \
|
|
ADC_IER_JEOC | ADC_IER_JEOS | ADC_IER_OVR)
|
|
|
|
/* Low-level ops helpers ****************************************************/
|
|
|
|
#define ADC_INT_ACK(adc, source) \
|
|
(adc)->llops->int_ack(adc, source)
|
|
#define ADC_INT_GET(adc) \
|
|
(adc)->llops->int_get(adc)
|
|
#define ADC_INT_ENABLE(adc, source) \
|
|
(adc)->llops->int_en(adc, source)
|
|
#define ADC_INT_DISABLE(adc, source) \
|
|
(adc)->llops->int_dis(adc, source)
|
|
#define ADC_REGDATA_GET(adc) \
|
|
(adc)->llops->val_get(adc)
|
|
#define ADC_INJDATA_GET(adc, chan) \
|
|
(adc)->llops->inj_get(adc, chan)
|
|
#define ADC_REG_STARTCONV(adc, state) \
|
|
(adc)->llops->reg_startconv(adc, state)
|
|
#define ADC_INJ_STARTCONV(adc, state) \
|
|
(adc)->llops->inj_startconv(adc, state)
|
|
#define ADC_OFFSET_SET(adc, ch, i, o) \
|
|
(adc)->llops->offset_set(adc, ch, i, o)
|
|
#define ADC_EXTSEL_SET(adc, extcfg) \
|
|
(adc)->llops->extsel_set(adc, extcfg)
|
|
#define ADC_DUMP_REGS(adc) \
|
|
(adc)->llops->dump_regs(adc)
|
|
|
|
#ifdef ADC_HAVE_DMA
|
|
# define ADC_REGBUF_REGISTER(adc, buffer, len) \
|
|
(adc)->llops->regbuf_reg(adc, buffer, len)
|
|
# define ADC_DMA_START(adc, cb, buf, len) \
|
|
(adc)->llops->dma_start(adc, cb, buf, len)
|
|
# define ADC_DMA_STOP(adc) \
|
|
(adc)->llops->dma_stop(adc)
|
|
#endif
|
|
|
|
/* IOCTL Commands ***********************************************************
|
|
*
|
|
* Cmd: ANIOC_STM32L4_TRIGGER_REG Arg:
|
|
* Cmd: ANIOC_STM32L4_TRIGGER_INJ Arg:
|
|
*
|
|
*/
|
|
|
|
#define ANIOC_STM32L4_TRIGGER_REG _ANIOC(AN_STM32L4_FIRST + 0)
|
|
#define ANIOC_STM32L4_TRIGGER_INJ _ANIOC(AN_STM32L4_FIRST + 1)
|
|
|
|
/****************************************************************************
|
|
* Public Types
|
|
****************************************************************************/
|
|
|
|
#ifdef CONFIG_STM32L4_ADC_LL_OPS
|
|
|
|
/* This structure provides the publicly visible representation of the
|
|
* "lower-half" ADC driver structure.
|
|
*/
|
|
|
|
struct stm32_adc_dev_s
|
|
{
|
|
/* Publicly visible portion of the "lower-half" ADC driver structure */
|
|
|
|
const struct stm32_adc_ops_s *llops;
|
|
|
|
/* Require cast-compatibility with private "lower-half" ADC structure */
|
|
};
|
|
|
|
/* Low-level operations for ADC */
|
|
|
|
struct stm32_adc_ops_s
|
|
{
|
|
/* Acknowledge interrupts */
|
|
|
|
void (*int_ack)(struct stm32_adc_dev_s *dev, uint32_t source);
|
|
|
|
/* Get pending interrupts */
|
|
|
|
uint32_t (*int_get)(struct stm32_adc_dev_s *dev);
|
|
|
|
/* Enable interrupts */
|
|
|
|
void (*int_en)(struct stm32_adc_dev_s *dev, uint32_t source);
|
|
|
|
/* Disable interrupts */
|
|
|
|
void (*int_dis)(struct stm32_adc_dev_s *dev, uint32_t source);
|
|
|
|
/* Get current ADC data register */
|
|
|
|
uint32_t (*val_get)(struct stm32_adc_dev_s *dev);
|
|
|
|
/* Start/stop regular conversion */
|
|
|
|
void (*reg_startconv)(struct stm32_adc_dev_s *dev, bool state);
|
|
|
|
/* Set offset for channel */
|
|
|
|
int (*offset_set)(struct stm32_adc_dev_s *dev, uint8_t ch, uint8_t i,
|
|
uint16_t offset);
|
|
|
|
/* Configure external event for regular group */
|
|
|
|
int (*extsel_set)(struct stm32_adc_dev_s *dev, uint32_t extcfg);
|
|
|
|
#ifdef ADC_HAVE_JEXTCFG
|
|
/* Configure the ADC external trigger for injected conversion */
|
|
|
|
void (*jextsel_set)(struct stm32_adc_dev_s *dev, uint32_t jextcfg);
|
|
#endif
|
|
|
|
#ifdef ADC_HAVE_INJECTED
|
|
/* Get current ADC injected data register */
|
|
|
|
uint32_t (*inj_get)(struct stm32_adc_dev_s *dev, uint8_t chan);
|
|
|
|
/* Start/stop injected conversion */
|
|
|
|
void (*inj_startconv)(struct stm32_adc_dev_s *dev, bool state);
|
|
#endif
|
|
|
|
#ifdef ADC_HAVE_DMA
|
|
/* Register buffer for ADC DMA transfer */
|
|
|
|
int (*regbuf_reg)(struct stm32_adc_dev_s *dev, uint16_t *buffer,
|
|
uint16_t len);
|
|
|
|
/* Start DMA */
|
|
|
|
void (*dma_start)(struct stm32_adc_dev_s *dev, dma_callback_t callback,
|
|
uint16_t *buffer, uint16_t len);
|
|
|
|
/* Stop DMA */
|
|
|
|
void (*dma_stop)(struct stm32_adc_dev_s *dev);
|
|
#endif
|
|
|
|
/* Dump ADC regs */
|
|
|
|
void (*dump_regs)(struct stm32_adc_dev_s *dev);
|
|
};
|
|
|
|
#endif /* CONFIG_STM32L4_ADC_LL_OPS */
|
|
|
|
/****************************************************************************
|
|
* Public Function Prototypes
|
|
****************************************************************************/
|
|
|
|
#ifndef __ASSEMBLY__
|
|
#ifdef __cplusplus
|
|
#define EXTERN extern "C"
|
|
extern "C"
|
|
{
|
|
#else
|
|
#define EXTERN extern
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Name: stm32l4_adc_initialize
|
|
*
|
|
* Description:
|
|
* Initialize the ADC.
|
|
*
|
|
* Input Parameters:
|
|
* intf - Could be {1,2,3} for ADC1, ADC2, or ADC3
|
|
* chanlist - The list of channels
|
|
* nchannels - Number of channels
|
|
*
|
|
* Returned Value:
|
|
* Valid ADC device structure reference on success; a NULL on failure
|
|
*
|
|
****************************************************************************/
|
|
|
|
struct adc_dev_s;
|
|
struct adc_dev_s *stm32l4_adc_initialize(int intf,
|
|
const uint8_t *chanlist,
|
|
int nchannels);
|
|
#undef EXTERN
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
#endif /* __ASSEMBLY__ */
|
|
|
|
#endif /* CONFIG_STM32L4_ADC1 || CONFIG_STM32L4_ADC2 || CONFIG_STM32L4_ADC3 */
|
|
#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_ADC_H */ |