104 lines
4.2 KiB
C
104 lines
4.2 KiB
C
/****************************************************************************
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* arch/arm/include/lpc31xx/irq.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* This file should never be included directly but, rather,
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* only indirectly through nuttx/irq.h
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*/
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#ifndef __ARCH_ARM_INCLUDE_LPC31XX_IRQ_H
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#define __ARCH_ARM_INCLUDE_LPC31XX_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* LPC31XX Interrupts */
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/* IRQ0: Reserved */
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#define LPC31_IRQ_IRQ0 0 /* IRQ1: Event router cascaded IRQ0 */
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#define LPC31_IRQ_IRQ1 1 /* IRQ2: Event router cascaded IRQ1 */
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#define LPC31_IRQ_IRQ2 2 /* IRQ3: Event router cascaded IRQ2 */
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#define LPC31_IRQ_IRQ3 3 /* IRQ4: Event router cascaded IRQ3 */
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#define LPC31_IRQ_TMR0 4 /* IRQ5: Timer 0 Interrupt */
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#define LPC31_IRQ_TMR1 5 /* IRQ6: Timer 1 Interrupt */
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#define LPC31_IRQ_TMR2 6 /* IRQ7: Timer 2 Interrupt */
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#define LPC31_IRQ_TMR3 7 /* IRQ8: Timer 3 Interrupt */
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#define LPC31_IRQ_ADC 8 /* IRQ9: ADC 10-bit */
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#define LPC31_IRQ_UART 9 /* IRQ10: UART */
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#define LPC31_IRQ_I2C0 10 /* IRQ11: I2C0 */
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#define LPC31_IRQ_I2C1 11 /* IRQ12: I2C1 */
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#define LPC31_IRQ_I2STX0 12 /* IRQ13: I2S0 Transmit */
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#define LPC31_IRQ_I2STX1 13 /* IRQ14: I2S1 Transmit */
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#define LPC31_IRQ_I2SRX0 14 /* IRQ15: I2S0 Receive */
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#define LPC31_IRQ_I2SRX1 15 /* IRQ16: I2S1 Receive */
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/* IRQ17: Reserved */
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#define LPC31_IRQ_LCD 17 /* IRQ18: LCD Interface */
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#define LPC31_IRQ_SPISMS 18 /* IRQ19: SPI SMS */
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#define LPC31_IRQ_SPITX 19 /* IRQ20: SPI Transmit */
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#define LPC31_IRQ_SPIRX 20 /* IRQ21: SPI Receive */
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#define LPC31_IRQ_SPIOVF 21 /* IRQ22: SPI Overflow */
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#define LPC31_IRQ_SPI 22 /* IRQ23: SPI */
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#define LPC31_IRQ_DMA 23 /* IRQ24: DMA */
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#define LPC31_IRQ_NAND 24 /* IRQ25: NAND FLASH Controller */
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#define LPC31_IRQ_MCI 25 /* IRQ26: MCI */
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#define LPC31_IRQ_USBOTG 26 /* IRQ27: USB OTG */
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#define LPC31_IRQ_ISRAM0 27 /* IRQ28: ISRAM0 MRC Finished */
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#define LPC31_IRQ_ISRAM1 28 /* IRQ29: ISRAM1 MRC Finished */
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#define LPC31_IRQ_SYSTIMER LPC31_IRQ_TMR0
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#define NR_IRQS (LPC31_IRQ_ISRAM1+1)
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Inline functions
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif /* __ARCH_ARM_INCLUDE_LPC31XX_IRQ_H */
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