zhuyanlin ec17cad69d arch:xtensa:include chip/irq.h instead of depend on chip config. ... Many duplicate code when more chips add-in, follow arch/arm/include/irq.h method, use chip/irq.h instead. Change-Id: I42f516c1dda68e973939c669f627c457cd0bc65e		2021-08-05 10:08:48 +02:00
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esp32	esp32: replace EPS32 typo with ESP32	2021-04-29 18:03:05 -03:00
esp32s2	Fix dangling whitespace at the end of line	2021-06-01 07:49:54 +02:00
lx6	arch: xtensa: Author Gregory Nutt: update licenses to Apache	2021-04-02 03:14:31 -05:00
lx7	Add initial ESP32S2 Xtensa support	2021-06-01 07:49:54 +02:00
xtensa	Add initial ESP32S2 Xtensa support	2021-06-01 07:49:54 +02:00
.gitignore	Remove exra whitespace from files (#189)	2020-01-31 09:24:49 -06:00
arch.h	arch: Rename xxx_getsp to up_getsp	2021-06-09 10:20:02 -07:00
elf.h	xtensa: Implement a few relocations	2020-03-16 07:54:49 -06:00
inttypes.h	xtensa inttypes.h: Remove PRI/SCN macros for fast and least types	2020-11-05 18:49:22 -08:00
irq.h	arch:xtensa:include chip/irq.h instead of depend on chip config.	2021-08-05 10:08:48 +02:00
limits.h	arch: xtensa: Author Gregory Nutt: update licenses to Apache	2021-04-02 03:14:31 -05:00
loadstore.h	esp32: emulate byte access for module text	2020-03-16 07:54:49 -06:00
simcall.h	xtensa: Implement simcall	2020-03-12 09:03:31 -05:00
spinlock.h	arch&boards/xtensa: Fix some typos, references to STM/ARM code and	2020-08-27 05:48:55 -07:00
syscall.h	arch: xtensa: Author Gregory Nutt: update licenses to Apache	2021-04-02 03:14:31 -05:00
tls.h	arch: Rename xxx_getsp to up_getsp	2021-06-09 10:20:02 -07:00
types.h	arch: xtensa: Author Gregory Nutt: update licenses to Apache	2021-04-02 03:14:31 -05:00