22cd0d47fa
This makes the user interface a little hostile. People thing of an MTU of 1500 bytes, but the corresponding packet is really 1514 bytes (including the 14 byte Ethernet header). A more friendly solution would configure the MTU (as before), but then derive the packet buffer size by adding the MAC header length. Instead, we define the packet buffer size then derive the MTU.
The MTU is not common currency in networking. On the wire, the only real issue is the MSS which is derived from MTU by subtracting the IP header and TCP header sizes (for the case of TCP). Now it is derived for the PKTSIZE by subtracting the IP header, the TCP header, and the MAC header sizes. So we should be all good and without the recurring 14 byte error in MTU's and MSS's.
Squashed commit of the following:
Trivial update to fix some spacing issues.
net/: Rename several macros containing _MTU to _PKTSIZE.
net/: Rename CONFIG_NET_SLIP_MTU to CONFIG_NET_SLIP_PKTSIZE and similarly for CONFIG_NET_TUN_MTU. These are not the MTU which does not include the size of the link layer header. These are the full size of the packet buffer memory (minus any GUARD bytes).
net/: Rename CONFIG_NET_6LOWPAN_MTU to CONFIG_NET_6LOWPAN_PKTSIZE and similarly for CONFIG_NET_TUN_MTU. These are not the MTU which does not include the size of the link layer header. These are the full size of the packet buffer memory (minus any GUARD bytes).
net/: Rename CONFIG_NET_ETH_MTU to CONFIG_NET_ETH_PKTSIZE. This is not the MTU which does not include the size of the link layer header. This is the full size of the packet buffer memory (minus any GUARD bytes).
net/: Rename the file d_mtu in the network driver structure to d_pktsize. That value saved there is not the MTU. The packetsize is the memory large enough to hold the maximum packet PLUS the size of the link layer header. The MTU does not include the link layer header.
502 lines
20 KiB
Plaintext
502 lines
20 KiB
Plaintext
README.txt
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==========
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This is the README file for the port of NuttX to the Freescale Kinetis
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TWR-K60N512. Refer to the Freescale web site for further information
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about this part:
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http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=TWR-K60N512-KIT
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The TWR-K60N51 includes with the FreeScale Tower System which provides (among
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other things) a simple UART connection.
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Contents
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========
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o Kinetis TWR-K60N512 Features
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o Kinetis TWR-K60N512 Pin Configuration
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- On-Board Connections
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- Connections via the General Purpose Tower Plug-in (TWRPI) Socket
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- Connections via the Tower Primary Connector Side A
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- Connections via the Tower Primary Connector Side B
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- TWR-SER Serial Board Connection
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o LEDs
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o TWR-K60N512-specific Configuration Options
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o Configurations
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Kinetis TWR-K60N512 Features:
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=============================
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o K60N512 in 144 MAPBGA, K60N512VMD100
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o Capacitive Touch Pads
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o Integrated, Open-Source JTAG
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o SD Card Slot
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o MMA7660 3-axis accelerometer
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o Tower Plug-In (TWRPI) Socket for expansion (sensors, etc.)
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o Touch TWRPI Socket adds support for various capacitive touch boards
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(e.g. keypads, rotary dials, sliders, etc.)
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o Tower connectivity for access to USB, Ethernet, RS232/RS485, CAN, SPI,
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I²C, Flexbus, etc.
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o Plus: Potentiometer, 4 LEDs, 2 pushbuttons, infrared port
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Kinetis TWR-K60N512 Pin Configuration
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=====================================
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On-Board Connections
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-------------------- ------------------------- -------- -------------------
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FEATURE CONNECTION PORT/PIN PIN FUNCTION
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-------------------- ------------------------- -------- -------------------
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OSJTAG USB-to-serial OSJTAG Bridge RX Data PTE9 UART5_RX
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Bridge OSJTAG Bridge TX Data PTE8 UART5_TX
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SD Card Slot SD Clock PTE2 SDHC0_DCLK
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SD Command PTE3 SDHC0_CMD
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SD Data0 PTE1 SDHC0_D0
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SD Data1 PTE0 SDHC0_D1
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SD Data2 PTE5 SDHC0_D2
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SD Data3 PTE4 SDHC0_D3
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SD Card Detect PTE28 PTE28
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SD Write Protect PTE27 PTE27
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Infrared Port IR Transmit PTD7 CMT_IRO
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IR Receive PTC6 CMP0_IN0
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Pushbuttons SW1 (IRQ0) PTA19 PTA19
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SW2 (IRQ1) PTE26 PTE26
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SW3 (RESET) RESET_b RESET_b
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Touch Pads E1 / Touch PTA4 TSI0_CH5
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E2 / Touch PTB3 TSI0_CH8
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E3 / Touch PTB2 TSI0_CH7
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E4 / Touch PTB16 TSI0_CH9
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LEDs E1 / Orange LED PTA11 PTA11
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E2 / Yellow LED PTA28 PTA28
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E3 / Green LED PTA29 PTA29
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E4 / Blue LED PTA10 PTA10
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Potentiometer Potentiometer (R71) ? ADC1_DM1
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Accelerometer I2C SDA PTD9 I2C0_SDA
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I2C SCL PTD8 I2C0_SCL
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IRQ PTD10 PTD10
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Touch Pad / Segment Electrode 0 (J3 Pin 3) PTB0 TSI0_CH0
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LCD TWRPI Socket Electrode 1 (J3 Pin 5) PTB1 TSI0_CH6
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Electrode 2 (J3 Pin 7) PTB2 TSI0_CH7
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Electrode 3 (J3 Pin 8) PTB3 TSI0_CH8
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Electrode 4 (J3 Pin 9) PTC0 TSI0_CH13
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Electrode 5 (J3 Pin 10) PTC1 TSI0_CH14
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Electrode 6 (J3 Pin 11) PTC2 TSI0_CH15
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Electrode 7 (J3 Pin 12) PTA4 TSI0_CH5
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Electrode 8 (J3 Pin 13) PTB16 TSI0_CH9
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Electrode 9 (J3 Pin 14) PTB17 TSI0_CH10
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Electrode 10 (J3 Pin 15) PTB18 TSI0_CH11
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Electrode 11 (J3 Pin 16) PTB19 TSI0_CH12
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TWRPI ID0 (J3 Pin 17) ? ADC1_DP1
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TWRPI ID1 (J3 Pin 18) ? ADC1_SE16
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Connections via the General Purpose Tower Plug-in (TWRPI) Socket
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-------------------- ------------------------- -------- -------------------
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FEATURE CONNECTION PORT/PIN PIN FUNCTION
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-------------------- ------------------------- -------- -------------------
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General Purpose TWRPI AN0 (J4 Pin 8) ? ADC0_DP0/ADC1_DP3
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TWRPI Socket TWRPI AN1 (J4 Pin 9) ? ADC0_DM0/ADC1_DM3
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TWRPI AN2 (J4 Pin 12) ? ADC1_DP0/ADC0_DP3
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TWRPI ID0 (J4 Pin 17) ? ADC0_DP1
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TWRPI ID1 (J4 Pin 18) ? ADC0_DM1
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TWRPI I2C SCL (J5 Pin 3) PTD8 I2C0_SCL
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TWRPI I2C SDA (J5 Pin 4) PTD9 I2C0_SDA
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TWRPI SPI MISO (J5 Pin 9) PTD14 SPI2_SIN
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TWRPI SPI MOSI (J5 Pin 10) PTD13 SPI2_SOUT
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TWRPI SPI SS (J5 Pin 11) PTD15 SPI2_PCS0
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TWRPI SPI CLK (J5 Pin 12) PTD12 SPI2_SCK
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TWRPI GPIO0 (J5 Pin 15) PTD10 PTD10
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TWRPI GPIO1 (J5 Pin 16) PTB8 PTB8
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TWRPI GPIO2 (J5 Pin 17) PTB9 PTB9
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TWRPI GPIO3 (J5 Pin 18) PTA19 PTA19
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TWRPI GPIO4 (J5 Pin 19) PTE26 PTE26
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The TWR-K60N512 features two expansion card-edge connectors that interface
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to the Primary and Secondary Elevator boards in a Tower system. The Primary
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Connector (comprised of sides A and B) is utilized by the TWR-K60N512 while
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the Secondary Connector (comprised of sides C and D) only makes connections
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to the GND pins.
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Connections via the Tower Primary Connector Side A
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--- -------------------- --------------------------------
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PIN NAME USAGE
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--- -------------------- --------------------------------
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A7 SCL0 PTD8
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A8 SDA0 PTD9
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A9 GPIO9 / CTS1 PTC19
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A10 GPIO8 / SDHC_D2 PTE5
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A11 GPIO7 / SD_WP_DET PTE27
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A13 ETH_MDC PTB1
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A14 ETH_MDIO PTB0
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A16 ETH_RXDV PTA14
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A19 ETH_RXD1 PTA12
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A20 ETH_RXD0 PTA13
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A21 SSI_MCLK PTE6
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A22 SSI_BCLK PTE12
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A23 SSI_FS PTE11
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A24 SSI_RXD PTE7
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A25 SSI_TXD PTE10
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A27 AN3 PGA0_DP/ADC0_DP0/ADC1_DP3
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A28 AN2 PGA0_DM/ADC0_DM0/ADC1_DM3
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A29 AN1 PGA1_DP/ADC1_DP0/ADC0_DP3
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A30 AN0 PGA1_DM/ADC1_DM0/ADC0_DM3
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A33 TMR1 PTA9
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A34 TMR0 PTA8
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A35 GPIO6 PTB9
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A37 PWM3 PTA6
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A38 PWM2 PTC3
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A39 PWM1 PTC2
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A40 PWM0 PTC1
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A41 RXD0 PTE25
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A42 TXD0 PTE24
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A43 RXD1 PTC16
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A44 TXD1 PTC17
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A64 CLKOUT0 PTC3
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A66 EBI_AD14 PTC0
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A67 EBI_AD13 PTC1
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A68 EBI_AD12 PTC2
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A69 EBI_AD11 PTC4
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A70 EBI_AD10 PTC5
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A71 EBI_AD9 PTC6
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A71 EBI_R/W_b PTC11
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A72 EBI_AD8 PTC7
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A73 EBI_AD7 PTC8
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A74 EBI_AD6 PTC9
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A75 EBI_AD5 PTC10
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A76 EBI_AD4 PTD2
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A77 EBI_AD3 PTD3
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A78 EBI_AD2 PTD4
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A79 EBI_AD1 PTD5
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A80 EBI_AD0 PTD6
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Connections via the Tower Primary Connector Side B
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--- -------------------- --------------------------------
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PIN NAME USAGE
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--- -------------------- --------------------------------
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B7 SDHC_CLK / SPI1_CLK PTE2
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B9 SDHC_D3 / SPI1_CS0_b PTE4
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B10 SDHC_CMD / SPI1_MOSI PTE1
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B11 SDHC_D0 / SPI1_MISO PTE3
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B13 ETH_RXER PTA5
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B15 ETH_TXEN PTA15
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B19 ETH_TXD1 PTA17
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B20 ETH_TXD0 PTA16
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B21 GPIO1 / RTS1 PTC18
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B22 GPIO2 / SDHC_D1 PTE0
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B23 GPIO3 PTE28
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B24 CLKIN0 PTA18
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B25 CLKOUT1 PTE26
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B27 AN7 PTB7
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B28 AN6 PTB6
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B29 AN5 PTB5
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B30 AN4 PTB4
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B34 TMR2 PTD6
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B35 GPIO4 PTB8
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B37 PWM7 PTA2
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B38 PWM6 PTA1
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B39 PWM5 PTD5
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B40 PWM4 PTA7
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B41 CANRX0 PTE25
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B42 CANTX0 PTE24
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B44 SPI0_MISO PTD14
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B45 SPI0_MOSI PTD13
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B46 SPI0_CS0_b PTD11
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B47 SPI0_CS1_b PTD15
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B48 SPI0_CLK PTD12
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B50 SCL1 PTD8
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B51 SDA1 PTD9
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B52 GPIO5 / SD_CARD_DET PTE28
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B55 IRQ_H PTA24
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B56 IRQ_G PTA24
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B57 IRQ_F PTA25
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B58 IRQ_E PTA25
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B59 IRQ_D PTA26
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B60 IRQ_C PTA26
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B61 IRQ_B PTA27
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B62 IRQ_A PTA27
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B63 EBI_ALE / EBI_CS1_b PTD0
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B64 EBI_CS0_b PTD1
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B66 EBI_AD15 PTB18
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B67 EBI_AD16 PTB17
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B68 EBI_AD17 PTB16
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B69 EBI_AD18 PTB11
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B70 EBI_AD19 PTB10
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B72 EBI_OE_b PTB19
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B73 EBI_D7 PTB20
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B74 EBI_D6 PTB21
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B75 EBI_D5 PTB22
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B76 EBI_D4 PTB23
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B77 EBI_D3 PTC12
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B78 EBI_D2 PTC13
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B79 EBI_D1 PTC14
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B80 EBI_D0 PTC15
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TWR-SER Serial Board Connection
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===============================
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The serial board connects into the tower and then maps to the tower pins to
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yet other functions (see TWR-SER.pdf).
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For the serial port, the following jumpers are required:
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J15: 1-2 (default)
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J17: 1-2 (default)
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J18: 1-2 (default)
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J19: 1-2 (default)
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The two connections map as follows:
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A41 RXD0 - Not connected
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A42 TXD0 - Not connected
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A43 RXD1 - ELE_RXD (connects indirectory to DB-9 connector J8)
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A44 TXD1 - ELE_TXD (connects indirectory to DB-9 connector J8)
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Finally, we can conclude that:
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UART4 (PTE24/25) is not connected, and
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UART3 (PTC16/17) is associated with the DB9 connector
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NOTE: UART5 is associated with OSJTAG bridge and may also be usable.
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LEDs
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====
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The TWR-K60N100 board has four LEDs labeled D2..D4 on the board. Usage of
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these LEDs is defined in include/board.h and src/up_leds.c. They are encoded
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as follows:
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SYMBOL Meaning LED1* LED2 LED3 LED4
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------------------- ----------------------- ------- ------- ------- ------
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LED_STARTED NuttX has been started ON OFF OFF OFF
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LED_HEAPALLOCATE Heap has been allocated OFF ON OFF OFF
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LED_IRQSENABLED Interrupts enabled ON ON OFF OFF
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LED_STACKCREATED Idle stack created OFF OFF ON OFF
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LED_INIRQ In an interrupt** ON N/C N/C OFF
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LED_SIGNAL In a signal handler*** N/C ON N/C OFF
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LED_ASSERTION An assertion failed ON ON N/C OFF
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LED_PANIC The system has crashed N/C N/C N/C ON
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LED_IDLE STM32 is is sleep mode (Optional, not used)
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* If LED1, LED2, LED3 are statically on, then NuttX probably failed to boot
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and these LEDs will give you some indication of where the failure was
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** The normal state is LED3 ON and LED1 faintly glowing. This faint glow
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is because of timer interrupts that result in the LED being illuminated
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on a small proportion of the time.
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*** LED2 may also flicker normally if signals are processed.
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TWR-K60N512-specific Configuration Options
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==========================================
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CONFIG_ARCH - Identifies the arch/ subdirectory. This sould
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be set to:
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CONFIG_ARCH=arm
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CONFIG_ARCH_family - For use in C code:
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CONFIG_ARCH_ARM=y
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CONFIG_ARCH_architecture - For use in C code:
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CONFIG_ARCH_CORTEXM4=y
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CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
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CONFIG_ARCH_CHIP=k40
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CONFIG_ARCH_CHIP_name - For use in C code to identify the exact
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chip:
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CONFIG_ARCH_CHIP_MK60N512VMD100
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CONFIG_ARCH_BOARD - Identifies the configs subdirectory and
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hence, the board that supports the particular chip or SoC.
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CONFIG_ARCH_BOARD=twr-k60n512 (for the TWR-K60N512 development board)
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CONFIG_ARCH_BOARD_name - For use in C code
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CONFIG_ARCH_BOARD_TWR_K60N512=y
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CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation
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of delay loops
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CONFIG_ENDIAN_BIG - define if big endian (default is little
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endian)
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CONFIG_RAM_SIZE - Describes the installed DRAM (SRAM in this case):
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CONFIG_RAM_SIZE=0x00010000 (64Kb)
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CONFIG_RAM_START - The start address of installed DRAM
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CONFIG_RAM_START=0x20000000
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CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that
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have LEDs
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CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
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stack. If defined, this symbol is the size of the interrupt
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stack in bytes. If not defined, the user task stacks will be
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used during interrupt handling.
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CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
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CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture.
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CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that
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cause a 100 second delay during boot-up. This 100 second delay
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serves no purpose other than it allows you to calibratre
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CONFIG_ARCH_LOOPSPERMSEC. You simply use a stop watch to measure
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the 100 second delay then adjust CONFIG_ARCH_LOOPSPERMSEC until
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the delay actually is 100 seconds.
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Individual subsystems can be enabled:
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CONFIG_KINETIS_TRACE -- Enable trace clocking on power up.
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CONFIG_KINETIS_FLEXBUS -- Enable flexbus clocking on power up.
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CONFIG_KINETIS_UART0 -- Support UART0
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CONFIG_KINETIS_UART1 -- Support UART1
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CONFIG_KINETIS_UART2 -- Support UART2
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CONFIG_KINETIS_UART3 -- Support UART3
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CONFIG_KINETIS_UART4 -- Support UART4
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CONFIG_KINETIS_UART5 -- Support UART5
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CONFIG_KINETIS_ENET -- Support Ethernet (K60 only)
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CONFIG_KINETIS_RNGB -- Support the random number generator(K60 only)
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CONFIG_KINETIS_FLEXCAN0 -- Support FlexCAN0
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CONFIG_KINETIS_FLEXCAN1 -- Support FlexCAN1
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CONFIG_KINETIS_SPI0 -- Support SPI0
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CONFIG_KINETIS_SPI1 -- Support SPI1
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CONFIG_KINETIS_SPI2 -- Support SPI2
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CONFIG_KINETIS_I2C0 -- Support I2C0
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CONFIG_KINETIS_I2C1 -- Support I2C1
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CONFIG_KINETIS_I2S -- Support I2S
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CONFIG_KINETIS_DAC0 -- Support DAC0
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CONFIG_KINETIS_DAC1 -- Support DAC1
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CONFIG_KINETIS_ADC0 -- Support ADC0
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CONFIG_KINETIS_ADC1 -- Support ADC1
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CONFIG_KINETIS_CMP -- Support CMP
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CONFIG_KINETIS_VREF -- Support VREF
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CONFIG_KINETIS_SDHC -- Support SD host controller
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CONFIG_KINETIS_FTM0 -- Support FlexTimer 0
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CONFIG_KINETIS_FTM1 -- Support FlexTimer 1
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CONFIG_KINETIS_FTM2 -- Support FlexTimer 2
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CONFIG_KINETIS_LPTMR0 -- Support the low power timer 0
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CONFIG_KINETIS_RTC -- Support RTC
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CONFIG_KINETIS_SLCD -- Support the segment LCD (K60 only)
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CONFIG_KINETIS_EWM -- Support the external watchdog
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CONFIG_KINETIS_CMT -- Support Carrier Modulator Transmitter
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CONFIG_KINETIS_USBOTG -- Support USB OTG (see also CONFIG_USBHOST and CONFIG_USBDEV)
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CONFIG_KINETIS_USBDCD -- Support the USB Device Charger Detection module
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CONFIG_KINETIS_LLWU -- Support the Low Leakage Wake-Up Unit
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CONFIG_KINETIS_TSI -- Support the touch screeen interface
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CONFIG_KINETIS_FTFL -- Support FLASH
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CONFIG_KINETIS_DMA -- Support DMA
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CONFIG_KINETIS_CRC -- Support CRC
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CONFIG_KINETIS_PDB -- Support the Programmable Delay Block
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CONFIG_KINETIS_PIT -- Support Programmable Interval Timers
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CONFIG_ARM_MPU -- Support the MPU
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Kinetis interrupt priorities (Default is the mid priority). These should
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not be set because they can cause unhandled, nested interrupts. All
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interrupts need to be at the default priority in the current design.
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CONFIG_KINETIS_UART0PRIO
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CONFIG_KINETIS_UART1PRIO
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CONFIG_KINETIS_UART2PRIO
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CONFIG_KINETIS_UART3PRIO
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CONFIG_KINETIS_UART4PRIO
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CONFIG_KINETIS_UART5PRIO
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CONFIG_KINETIS_EMACTMR_PRIO
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CONFIG_KINETIS_EMACTX_PRIO
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CONFIG_KINETIS_EMACRX_PRIO
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CONFIG_KINETIS_EMACMISC_PRIO
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CONFIG_KINETIS_SDHC_PRIO
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PIN Interrupt Support
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CONFIG_KINETIS_GPIOIRQ -- Enable pin interrupt support. Also needs
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one or more of the following:
|
|
CONFIG_KINETIS_PORTAINTS -- Support 32 Port A interrupts
|
|
CONFIG_KINETIS_PORTBINTS -- Support 32 Port B interrupts
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|
CONFIG_KINETIS_PORTCINTS -- Support 32 Port C interrupts
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|
CONFIG_KINETIS_PORTDINTS -- Support 32 Port D interrupts
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|
CONFIG_KINETIS_PORTEINTS -- Support 32 Port E interrupts
|
|
|
|
Kinetis K60 specific device driver settings
|
|
|
|
CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn (n=0..5) for the
|
|
console and ttys0 (default is the UART0).
|
|
CONFIG_UARTn_RXBUFSIZE - Characters are buffered as received.
|
|
This specific the size of the receive buffer
|
|
CONFIG_UARTn_TXBUFSIZE - Characters are buffered before
|
|
being sent. This specific the size of the transmit buffer
|
|
CONFIG_UARTn_BAUD - The configure BAUD of the UART.
|
|
CONFIG_UARTn_BITS - The number of bits. Must be either 8 or 8.
|
|
CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
|
|
|
|
Kenetis ethernet controller settings
|
|
|
|
CONFIG_ENET_NRXBUFFERS - Number of RX buffers. The size of one
|
|
buffer is determined by CONFIG_NET_ETH_PKTSIZE. Default: 6
|
|
CONFIG_ENET_NTXBUFFERS - Number of TX buffers. The size of one
|
|
buffer is determined by CONFIG_NET_ETH_PKTSIZE. Default: 2
|
|
CONFIG_ENET_USEMII - Use MII mode. Default: RMII mode.
|
|
CONFIG_ENET_PHYADDR - PHY address
|
|
|
|
Configurations
|
|
==============
|
|
|
|
Each TWR-K60N512 configuration is maintained in a sub-directory and
|
|
can be selected as follow:
|
|
|
|
tools/configure.sh twr-k60n512/<subdir>
|
|
|
|
Where <subdir> is one of the following:
|
|
|
|
nsh:
|
|
---
|
|
Configures the NuttShell (nsh) located at apps/examples/nsh. The
|
|
Configuration enables both the serial and telnet NSH interfaces.
|
|
Support for the board's SPI-based MicroSD card is included
|
|
(but not passing tests as of this writing).
|
|
|
|
NOTES:
|
|
|
|
1. This configuration uses the mconf-based configuration tool. To
|
|
change this configuration using that tool, you should:
|
|
|
|
a. Build and install the kconfig-mconf tool. See nuttx/README.txt
|
|
see additional README.txt files in the NuttX tools repository.
|
|
|
|
b. Execute 'make menuconfig' in nuttx/ in order to start the
|
|
reconfiguration process.
|
|
|
|
2. Default platform/toolchain:
|
|
|
|
CONFIG_HOST_LINUX=y : Linux (Cygwin under Windows okay too).
|
|
CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : Buildroot (arm-nuttx-elf-gcc)
|
|
CONFIG_ARMV7M_OABI_TOOLCHAIN=y : The older OABI version
|
|
CONFIG_RAW_BINARY=y : Output formats: ELF and raw binary
|
|
|
|
3. An SDHC driver is under work and can be enabled in the NSH configuration
|
|
for further testing be setting the following configuration values as
|
|
follows:
|
|
|
|
CONFIG_KINETIS_SDHC=y : Enable the SDHC driver
|
|
|
|
CONFIG_MMCSD=y : Enable MMC/SD support
|
|
CONFIG_MMCSD_SDIO=y : Use the SDIO-based MMC/SD driver
|
|
CONFIG_MMCSD_NSLOTS=1 : One MMC/SD slot
|
|
|
|
CONFIG_FAT=y : Eable FAT file system
|
|
CONFIG_FAT_LCNAMES=y : FAT lower case name support
|
|
CONFIG_FAT_LFN=y : FAT long file name support
|
|
CONFIG_FAT_MAXFNAME=32 : Maximum lenght of a long file name
|
|
|
|
CONFIG_KINETIS_GPIOIRQ=y : Enable GPIO interrupts
|
|
CONFIG_KINETIS_PORTEINTS=y : Enable PortE GPIO interrupts
|
|
|
|
CONFIG_SCHED_WORKQUEUE=y : Enable the NuttX workqueue
|
|
|
|
CONFIG_NSH_ARCHINIT=y : Provide NSH initializeation logic
|