4c601faf6f
Squashed commit of the following:
arch/arm/src/stm32f0l0: Various changes for a clean compilation. Still does not compile correctly due to missing FLASH latency definitions.
arch/arm/src/stm32f0l0/hardware: Add framework for the STM32 L0. Currently set to same as the STM32F0.
arch/arm/src/stm32f0l0/hardware: Very fragmentary FLASH header register definitions for the STM32 L0.
arch/arm/src/stm32f0l0: Bring in DMA v1. Cannot possibly be functionaly yet due to the limited number for M0 interrupts.
arch/arm/src/stm32f0l0: Add STM32 F0/L0 LSE and backup power domain controls.
arch/arm/src/stm32f0l0/hardware/stm32l0_pwr.h: Add STM32L0 PWR header file.
arch/arm/include/stm32f0l0/chip.h: Clean up WIP chip header file.
arch/arm/include/stm32f0l0/chip.h: WIP.
arm/src/stm32f0l0: Resolve some small differences between F0 and L0 GPIO pin options.
arch/arm/src/stm32f0l0: Better integrate STM32L0 header files.
nuttx/arch/arm/include/stm32f0l0: Add STM32L0 IRQ number definition file.
arch/arm/src/stm32f0l0: Add STM32L0 RCC driver.
arch/arm/src/stm32f0l0/hardware: Adds basic STM32L0 header files.
arch/arm/src/stm32f0l0: Add STM32L0 chip selections.
configs/: Hook new STM32L0 boards into the configuration system.
configs: nucleo boards use as default ST LINK MCO as clock input from MCU and for this HSEBYP must be enabled
configs: add basic support for nucleo-l073rz
configs: add basic support for b-l072z-lrwan1
129 lines
6.1 KiB
C
129 lines
6.1 KiB
C
/****************************************************************************
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* arch/arm/include/stm32f0l0/stm32f0_irq.h
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*
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* Copyright (C) 2017 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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* Alan Carvalho de Assis <acassis@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/* This file should never be included directed but, rather, only indirectly
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* through nuttx/irq.h
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*/
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#ifndef __ARCH_ARM_INCLUDE_STM32F0L0_STM32F0_IRQ_H
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#define __ARCH_ARM_INCLUDE_STM32F0L0_STM32F0_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/irq.h>
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#include <arch/stm32f0l0/chip.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
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* bits in the NVIC. This does, however, waste several words of memory in the IRQ
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* to handle mapping tables.
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*
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* Processor Exceptions (vectors 0-15). These common definitions can be found
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* in nuttx/arch/arm/include/stm32f0l0/irq.h
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*/
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#define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: WWDG */
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#define STM32_IRQ_PVD_VDDIO2 (STM32_IRQ_EXTINT + 1) /* 1: PVD_VDDIO2 */
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#define STM32_IRQ_RTC (STM32_IRQ_EXTINT + 2) /* 2: RTC */
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#define STM32_IRQ_FLASH (STM32_IRQ_EXTINT + 3) /* 3: FLASH */
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#define STM32_IRQ_RCC_CRS (STM32_IRQ_EXTINT + 4) /* 4: RCC and CRS */
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#define STM32_IRQ_EXTI0_1 (STM32_IRQ_EXTINT + 5) /* 5: EXTI0_1 */
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#define STM32_IRQ_EXTI2_3 (STM32_IRQ_EXTINT + 6) /* 6: EXTI2_3 */
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#define STM32_IRQ_EXTI4_15 (STM32_IRQ_EXTINT + 7) /* 7: EXTI4_15 */
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#define STM32_IRQ_TSC (STM32_IRQ_EXTINT + 8) /* 8: TSC */
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#define STM32_IRQ_DMA_CH1 (STM32_IRQ_EXTINT + 9) /* 9: DMA_CH1 */
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#define STM32_IRQ_DMA_CH23 (STM32_IRQ_EXTINT + 10) /* 0: DMA_CH2_3 and DMA2_CH1_2 */
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#define STM32_IRQ_DMA_CH4567 (STM32_IRQ_EXTINT + 11) /* 1: DMA_CH4_5_6_7 and DMA2_CH3_4_5 */
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#define STM32_IRQ_ADC_COMP (STM32_IRQ_EXTINT + 12) /* 2: ADC_COMP */
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#define STM32_IRQ_TIM1_BRK (STM32_IRQ_EXTINT + 13) /* 3: TIM1_BRK_UP_TRG_COM */
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#define STM32_IRQ_TIM1_CC (STM32_IRQ_EXTINT + 14) /* 4: TIM1_CC */
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#define STM32_IRQ_TIM2 (STM32_IRQ_EXTINT + 15) /* 5: TIM2 */
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#define STM32_IRQ_TIM3 (STM32_IRQ_EXTINT + 16) /* 6: TIM3 */
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#define STM32_IRQ_TIM6_DAC (STM32_IRQ_EXTINT + 17) /* 7: TIM6 and DAC */
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#define STM32_IRQ_TIM7 (STM32_IRQ_EXTINT + 18) /* 8: TIM7 */
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#define STM32_IRQ_TIM14 (STM32_IRQ_EXTINT + 19) /* 9: TIM14 */
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#define STM32_IRQ_TIM15 (STM32_IRQ_EXTINT + 20) /* 0: TIM15 */
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#define STM32_IRQ_TIM16 (STM32_IRQ_EXTINT + 21) /* 1: TIM16 */
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#define STM32_IRQ_TIM17 (STM32_IRQ_EXTINT + 22) /* 2: TIM17 */
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#define STM32_IRQ_I2C1 (STM32_IRQ_EXTINT + 23) /* 3: I2C1 */
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#define STM32_IRQ_I2C2 (STM32_IRQ_EXTINT + 24) /* 4: I2C2 */
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#define STM32_IRQ_SPI1 (STM32_IRQ_EXTINT + 25) /* 5: SPI1 */
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#define STM32_IRQ_SPI2 (STM32_IRQ_EXTINT + 26) /* 6: SPI2 */
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#define STM32_IRQ_USART1 (STM32_IRQ_EXTINT + 27) /* 7: USART1 */
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#define STM32_IRQ_USART2 (STM32_IRQ_EXTINT + 28) /* 8: USART2 */
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#define STM32_IRQ_USART345678 (STM32_IRQ_EXTINT + 29) /* 9: USART3_4_5_6_7_8 */
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#define STM32_IRQ_CEC_CAN (STM32_IRQ_EXTINT + 30) /* 0: HDMI CEC and CAN */
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#define STM32_IRQ_USB (STM32_IRQ_EXTINT + 31) /* 1: USB */
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#define STM32_IRQ_NEXTINT (32) /* 32 external interrupts */
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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typedef void (*vic_vector_t)(uint32_t *regs);
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/****************************************************************************
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* Inline functions
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM_INCLUDE_STM32F0L0_STM32F0_IRQ_H */
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