187 lines
4.2 KiB
C
187 lines
4.2 KiB
C
/****************************************************************************
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* boards/arm/s32k1xx/s32k148evb/src/s32k1xx_periphclocks.c
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*
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* Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2018 NXP
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* All rights reserved.
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*
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* THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "s32k14x/s32k14x_clocknames.h"
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#include "s32k1xx_periphclocks.h"
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#include "s32k148evb.h"
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/* Each S32K1XX board must provide the following initialized structure.
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* This is needed to establish the initial peripheral clocking.
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*/
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const struct peripheral_clock_config_s g_peripheral_clockconfig0[] =
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{
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{
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.clkname = ENET0_CLK,
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#ifdef CONFIG_S32K1XX_ENET
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.clkgate = true,
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#else
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.clkgate = false,
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#endif
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.clksrc = CLK_SRC_FIRC_DIV1,
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.frac = MULTIPLY_BY_ONE,
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.divider = 1,
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},
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{
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.clkname = FLEXCAN0_CLK,
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#ifdef CONFIG_S32K1XX_FLEXCAN0
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.clkgate = true,
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#else
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.clkgate = false,
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#endif
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},
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{
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.clkname = FLEXCAN1_CLK,
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#ifdef CONFIG_S32K1XX_FLEXCAN1
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.clkgate = true,
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#else
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.clkgate = false,
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#endif
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},
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{
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.clkname = FLEXCAN2_CLK,
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#ifdef CONFIG_S32K1XX_FLEXCAN2
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.clkgate = true,
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#else
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.clkgate = false,
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#endif
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},
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{
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.clkname = LPI2C0_CLK,
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#ifdef CONFIG_S32K1XX_LPI2C0
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.clkgate = true,
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#else
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.clkgate = false,
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#endif
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.clksrc = CLK_SRC_SIRC_DIV2,
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},
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{
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.clkname = LPI2C1_CLK,
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#ifdef CONFIG_S32K1XX_LPI2C1
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.clkgate = true,
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#else
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.clkgate = false,
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#endif
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.clksrc = CLK_SRC_SIRC_DIV2,
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},
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{
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.clkname = LPSPI0_CLK,
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#ifdef CONFIG_S32K1XX_LPSPI0
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.clkgate = true,
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#else
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.clkgate = false,
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#endif
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.clksrc = CLK_SRC_SIRC_DIV2,
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},
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{
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.clkname = LPSPI1_CLK,
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#ifdef CONFIG_S32K1XX_LPSPI1
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.clkgate = true,
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#else
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.clkgate = false,
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#endif
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.clksrc = CLK_SRC_SIRC_DIV2,
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},
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{
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.clkname = LPSPI2_CLK,
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#ifdef CONFIG_S32K1XX_LPSPI2
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.clkgate = true,
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#else
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.clkgate = false,
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#endif
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.clksrc = CLK_SRC_SIRC_DIV2,
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},
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{
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.clkname = LPUART0_CLK,
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#ifdef CONFIG_S32K1XX_LPUART0
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.clkgate = true,
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#else
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.clkgate = false,
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#endif
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.clksrc = CLK_SRC_SIRC_DIV2,
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},
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{
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.clkname = LPUART1_CLK,
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#ifdef CONFIG_S32K1XX_LPUART1
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.clkgate = true,
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#else
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.clkgate = false,
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#endif
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.clksrc = CLK_SRC_SIRC_DIV2,
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},
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{
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.clkname = LPUART2_CLK,
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#ifdef CONFIG_S32K1XX_LPUART2
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.clkgate = true,
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#else
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.clkgate = false,
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#endif
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.clksrc = CLK_SRC_SIRC_DIV2,
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},
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{
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.clkname = PORTA_CLK,
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.clkgate = true,
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},
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{
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.clkname = PORTB_CLK,
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.clkgate = true,
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},
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{
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.clkname = PORTC_CLK,
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.clkgate = true,
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},
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{
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.clkname = PORTD_CLK,
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.clkgate = true,
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},
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{
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.clkname = PORTE_CLK,
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.clkgate = true,
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},
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{
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.clkname = RTC0_CLK,
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#ifdef CONFIG_S32K1XX_RTC
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.clkgate = true,
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#else
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.clkgate = false,
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#endif
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},
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};
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unsigned int const num_of_peripheral_clocks_0 =
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sizeof(g_peripheral_clockconfig0) /
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sizeof(g_peripheral_clockconfig0[0]);
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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