f091c87e34
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1172 42af7a65-404d-4744-a932-0658087f49c3
460 lines
20 KiB
C
460 lines
20 KiB
C
/************************************************************************************
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* arch/sh/include/sh1/irq.h
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*
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* Copyright (C) 2008 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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/* This file should never be included directed but, rather,
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* only indirectly through nuttx/irq.h
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*/
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#ifndef __ARCH_SH_INCLUDE_SH1_IRQ_H
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#define __ARCH_SH_INCLUDE_SH1_IRQ_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* IRQ channels */
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/* Illegal instructions / Address errors */
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#define SH1_INVINSTR_IRQ (0) /* General invalid instruction */
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#define SH1_INVSLOT_IRQ (1) /* Invalid slot instruction */
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#define SH1_BUSERR_IRQ (2) /* CPU bus error */
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#define SH1_DMAERR_IRQ (3) /* DMA bus error */
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#define SH1_NMI_IRQ (4) /* NMI */
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#define SH1_USRBRK_IRQ (6) /* User break */
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/* Support for traps can be provided by simply enabling the following and
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* implementing the stubs to catch the interrupts
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*/
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#if 0
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# define SH1_TRAP_IRQ (7) /* TRAPA instruction (user break) */
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# define SH1_TRAP0_IRQ (SH1_TRAP_IRQ+0) /* TRAPA instruction (user break) */
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# define SH1_TRAP1_IRQ (SH1_TRAP_IRQ+1) /* " " " " " " " " */
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# define SH1_TRAP2_IRQ (SH1_TRAP_IRQ+2) /* " " " " " " " " */
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# define SH1_TRAP3_IRQ (SH1_TRAP_IRQ+3) /* " " " " " " " " */
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# define SH1_TRAP4_IRQ (SH1_TRAP_IRQ+4) /* " " " " " " " " */
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# define SH1_TRAP5_IRQ (SH1_TRAP_IRQ+5) /* " " " " " " " " */
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# define SH1_TRAP6_IRQ (SH1_TRAP_IRQ+6) /* " " " " " " " " */
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# define SH1_TRAP7_IRQ (SH1_TRAP_IRQ+7) /* " " " " " " " " */
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# define SH1_TRAP8_IRQ (SH1_TRAP_IRQ+8) /* " " " " " " " " */
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# define SH1_TRAP9_IRQ (SH1_TRAP_IRQ+9) /* " " " " " " " " */
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# define SH1_TRAP10_IRQ (SH1_TRAP_IRQ+10) /* " " " " " " " " */
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# define SH1_TRAP11_IRQ (SH1_TRAP_IRQ+11) /* " " " " " " " " */
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# define SH1_TRAP12_IRQ (SH1_TRAP_IRQ+12) /* " " " " " " " " */
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# define SH1_TRAP13_IRQ (SH1_TRAP_IRQ+13) /* " " " " " " " " */
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# define SH1_TRAP14_IRQ (SH1_TRAP_IRQ+14) /* " " " " " " " " */
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# define SH1_TRAP15_IRQ (SH1_TRAP_IRQ+15) /* " " " " " " " " */
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# define SH1_TRAP16_IRQ (SH1_TRAP_IRQ+16) /* " " " " " " " " */
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# define SH1_TRAP17_IRQ (SH1_TRAP_IRQ+17) /* " " " " " " " " */
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# define SH1_TRAP18_IRQ (SH1_TRAP_IRQ+18) /* " " " " " " " " */
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# define SH1_TRAP19_IRQ (SH1_TRAP_IRQ+19) /* " " " " " " " " */
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# define SH1_TRAP20_IRQ (SH1_TRAP_IRQ+20) /* " " " " " " " " */
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# define SH1_TRAP21_IRQ (SH1_TRAP_IRQ+21) /* " " " " " " " " */
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# define SH1_TRAP22_IRQ (SH1_TRAP_IRQ+22) /* " " " " " " " " */
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# define SH1_TRAP23_IRQ (SH1_TRAP_IRQ+23) /* " " " " " " " " */
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# define SH1_TRAP24_IRQ (SH1_TRAP_IRQ+24) /* " " " " " " " " */
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# define SH1_TRAP25_IRQ (SH1_TRAP_IRQ+25) /* " " " " " " " " */
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# define SH1_TRAP26_IRQ (SH1_TRAP_IRQ+26) /* " " " " " " " " */
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# define SH1_TRAP27_IRQ (SH1_TRAP_IRQ+27) /* " " " " " " " " */
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# define SH1_TRAP28_IRQ (SH1_TRAP_IRQ+28) /* " " " " " " " " */
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# define SH1_TRAP29_IRQ (SH1_TRAP_IRQ+29) /* " " " " " " " " */
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# define SH1_TRAP30_IRQ (SH1_TRAP_IRQ+30) /* " " " " " " " " */
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# define SH1_TRAP31_IRQ (SH1_TRAP_IRQ+31) /* " " " " " " " " */
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# define SH1_LASTTRAP_IRQ SH1_TRAP31_IRQ
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#else
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# define SH1_LASTTRAP_IRQ (6)
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#endif
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/* Interrupts */
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#define SH1_IRQ_IRQ (SH1_LASTTRAP_IRQ+1) /* IRQ0-7 */
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#define SH1_IRQ0_IRQ (SH1_IRQ_IRQ+0) /* IRQ0 */
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#define SH1_IRQ1_IRQ (SH1_IRQ_IRQ+1) /* IRQ1 */
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#define SH1_IRQ2_IRQ (SH1_IRQ_IRQ+2) /* IRQ2 */
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#define SH1_IRQ3_IRQ (SH1_IRQ_IRQ+3) /* IRQ3 */
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#define SH1_IRQ4_IRQ (SH1_IRQ_IRQ+4) /* IRQ4 */
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#define SH1_IRQ5_IRQ (SH1_IRQ_IRQ+5) /* IRQ5 */
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#define SH1_IRQ6_IRQ (SH1_IRQ_IRQ+6) /* IRQ6 */
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#define SH1_IRQ7_IRQ (SH1_IRQ_IRQ+7) /* IRQ7 */
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#define SH1_LASTIRQ_IRQ SH1_IRQ7_IRQ
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/* On-chip modules -- The following may be unique to the 7032 */
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#ifdef CONFIG_ARCH_SH7032
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/* DMAC */
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#define SH1_DMAC0_IRQ (SH1_LASTIRQ_IRQ+1) /* DMAC0 */
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#define SH1_DEI0_IRQ SH1_DMAC0_IRQ /* DEI0 */
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#define SH1_DMAC1_IRQ (SH1_LASTIRQ_IRQ+2) /* DMAC1 */
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#define SH1_DEI1_IRQ SH1_DMAC1_IRQ /* DEI1 */
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#define SH1_DMAC2_IRQ (SH1_LASTIRQ_IRQ+3) /* DMAC2 */
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#define SH1_DEI2_IRQ SH1_DMAC2_IRQ /* DEI2 */
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#define SH1_DMAC3_IRQ (SH1_LASTIRQ_IRQ+4) /* DMAC3 */
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#define SH1_DEI3_IRQ SH1_DMAC3_IRQ /* DEI3 */
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#define SH1_LASTDMAC_IRQ SH1_DEI3_IRQ
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/* ITU */
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#define SH1_ITU0_IRQ (SH1_LASTDMAC_IRQ+1) /* ITU0 */
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#define SH1_IMIA0_IRQ (SH1_ITU0_IRQ+0) /* IMIA0 */
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#define SH1_IMIBO_IRQ (SH1_ITU0_IRQ+1) /* IMIB0 */
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#define SH1_OVI0_IRQ (SH1_ITU0_IRQ+2) /* OVI0 */
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#define SH1_ITU1_IRQ (SH1_LASTDMAC_IRQ+4) /* ITU1 */
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#define SH1_IMIA1_IRQ (SH1_ITU1_IRQ+0) /* IMIA1 */
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#define SH1_IMIB1_IRQ (SH1_ITU1_IRQ+1) /* IMIB1 */
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#define SH1_OVI1_IRQ (SH1_ITU1_IRQ+2) /* OVI1 */
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#define SH1_ITU2_IRQ (SH1_LASTDMAC_IRQ+7) /* ITU2 */
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#define SH1_IMIA2_IRQ (SH1_ITU2_IRQ+0) /* IMIA2 */
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#define SH1_IMIB2_IRQ (SH1_ITU2_IRQ+1) /* IMIB2 */
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#define SH1_OVI2_IRQ (SH1_ITU2_IRQ+2) /* OVI2 */
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#define SH1_ITU3_IRQ (SH1_LASTDMAC_IRQ+10) /* ITU3 */
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#define SH1_IMIA3_IRQ (SH1_ITU3_IRQ+0) /* IMIA3 */
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#define SH1_IMIB3_IRQ (SH1_ITU3_IRQ+1) /* IMIB3 */
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#define SH1_OVI3_IRQ (SH1_ITU3_IRQ+2) /* OVI3 */
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#define SH1_ITU4_IRQ (SH1_LASTDMAC_IRQ+13) /* ITU4 */
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#define SH1_IMIA4_IRQ (SH1_ITU4_IRQ+0) /* IMIA4 */
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#define SH1_IMIB4_IRQ (SH1_ITU4_IRQ+1) /* IMIB4 */
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#define SH1_OVI4_IRQ (SH1_ITU4_IRQ+2) /* OVI4 */
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#define SH1_LASTITU_IRQ (SH1_LASTDMAC_IRQ+15)
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/* SCI */
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#define SH1_ERI_IRQ_OFFSET (0) /* ERI0 */
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#define SH1_RXI_IRQ_OFFSET (1) /* RxI0 */
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#define SH1_TXI_IRQ_OFFSET (2) /* TxI0 */
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#define SH1_TEI_IRQ_OFFSET (3) /* TEI0 */
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#define SH1_SCI_NIRQS (4)
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#define SH1_SCI0_IRQ (SH1_LASTITU_IRQ+1) /* SCI0 */
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#define SH1_ERI0_IRQ (SH1_SCI0_IRQ+SH1_ERI_IRQ_OFFSET) /* ERI0 */
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#define SH1_RXI0_IRQ (SH1_SCI0_IRQ+SH1_RXI_IRQ_OFFSET) /* RxI0 */
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#define SH1_TXI0_IRQ (SH1_SCI0_IRQ+SH1_TXI_IRQ_OFFSET) /* TxI0 */
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#define SH1_TEI0_IRQ (SH1_SCI0_IRQ+SH1_TEI_IRQ_OFFSET) /* TEI0 */
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#define SH1_SCI1_IRQ (SH1_SCI0_IRQ+SH1_SCI_NIRQS) /* SCI1 */
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#define SH1_ERI1_IRQ (SH1_SCI1_IRQ+SH1_ERI_IRQ_OFFSET) /* ERI1 */
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#define SH1_RXI1_IRQ (SH1_SCI1_IRQ+SH1_RXI_IRQ_OFFSET) /* RxI1 */
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#define SH1_TXI1_IRQ (SH1_SCI1_IRQ+SH1_TXI_IRQ_OFFSET) /* TxI1 */
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#define SH1_TEI1_IRQ (SH1_SCI1_IRQ+SH1_TEI_IRQ_OFFSET) /* TEI1 */
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#define SH1_LASTSCI_IRQ (SH1_SCI1_IRQ+SH1_SCI_NIRQS)
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#define SH1_PEI_IRQ (SH1_LASTSCI_IRQ+1) /* Parity control unit PEI */
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#define SH1_ADITI_IRQ (SH1_LASTSCI_IRQ+2) /* A/D ITI */
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#define SH1_WDTITI_IRQ (SH1_LASTSCI_IRQ+3) /* WDT ITI */
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#define SH1_CMI_IRQ (SH1_LASTSCI_IRQ+4) /* REF CMI */
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#define STR71X_IRQ_SYSTIMER STR71X_IRQ_T0TIMI
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#define NR_IRQS (SH1_CMI_IRQ+1)
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#endif
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/* Vector table offets **************************************************************/
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/* Resets */
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#define SH1_PWRONPC_VECOFFSET (0*4) /* 0: Power-on reset (hard, NMI high) PC*/
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#define SH1_PWRONSP_VECOFFSET (1*4) /* 1: Power-on reset (hard, NMI high) SP */
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#define SH1_MRESETPC_VECOFFSET (2*4) /* 2: Power-on reset (hard, NMI high) PC*/
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#define SH1_MRESETSP_VECOFFSET (3*4) /* 3: Power-on reset (hard, NMI high) SP */
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/* Illegal instructions / Address errors */
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#define SH1_INVINSTR_VECOFFSET (4*4) /* 4: General invalid instruction */
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/* 5: Reserved for system */
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#define SH1_INVSLOT_VECOFFSET (6*4) /* 6: Invalid slot instruction */
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/* 7-8: Reserved for system */
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#define SH1_BUSERR_VECOFFSET (9*4) /* 9: CPU bus error */
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#define SH1_DMAERR_VECOFFSET (10*4) /* 10: DMA bus error */
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/* NMI, user break */
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#define SH1_NMI_VECOFFSET (11*4) /* 11: NMI */
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#define SH1_USRBRK_VECOFFSET (12*4) /* 12: User break */
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/* 13-31: Reserved for system */
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/* Trap instruction */
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#define SH1_TRAP_VECOFFSET (32*4) /* 32-63: TRAPA instruction (user break) */
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#define SH1_TRAP0_VECOFFSET (32*4) /* 32: TRAPA instruction (user break) */
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#define SH1_TRAP1_VECOFFSET (33*4) /* 33: " " " " " " " " */
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#define SH1_TRAP2_VECOFFSET (34*4) /* 34: " " " " " " " " */
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#define SH1_TRAP3_VECOFFSET (35*4) /* 35: " " " " " " " " */
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#define SH1_TRAP4_VECOFFSET (36*4) /* 36: " " " " " " " " */
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#define SH1_TRAP5_VECOFFSET (37*4) /* 37: " " " " " " " " */
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#define SH1_TRAP6_VECOFFSET (38*4) /* 38: " " " " " " " " */
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#define SH1_TRAP7_VECOFFSET (39*4) /* 39: " " " " " " " " */
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#define SH1_TRAP8_VECOFFSET (40*4) /* 40: " " " " " " " " */
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#define SH1_TRAP9_VECOFFSET (41*4) /* 41: " " " " " " " " */
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#define SH1_TRAP10_VECOFFSET (42*4) /* 42: " " " " " " " " */
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#define SH1_TRAP11_VECOFFSET (43*4) /* 43: " " " " " " " " */
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#define SH1_TRAP12_VECOFFSET (44*4) /* 44: " " " " " " " " */
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#define SH1_TRAP13_VECOFFSET (45*4) /* 45: " " " " " " " " */
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#define SH1_TRAP14_VECOFFSET (46*4) /* 46: " " " " " " " " */
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#define SH1_TRAP15_VECOFFSET (47*4) /* 47: " " " " " " " " */
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#define SH1_TRAP16_VECOFFSET (48*4) /* 48: " " " " " " " " */
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#define SH1_TRAP17_VECOFFSET (49*4) /* 49: " " " " " " " " */
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#define SH1_TRAP18_VECOFFSET (50*4) /* 50: " " " " " " " " */
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#define SH1_TRAP19_VECOFFSET (51*4) /* 51: " " " " " " " " */
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#define SH1_TRAP20_VECOFFSET (52*4) /* 52: " " " " " " " " */
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#define SH1_TRAP21_VECOFFSET (53*4) /* 53: " " " " " " " " */
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#define SH1_TRAP22_VECOFFSET (54*4) /* 54: " " " " " " " " */
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#define SH1_TRAP23_VECOFFSET (55*4) /* 55: " " " " " " " " */
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#define SH1_TRAP24_VECOFFSET (56*4) /* 56: " " " " " " " " */
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#define SH1_TRAP25_VECOFFSET (57*4) /* 57: " " " " " " " " */
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#define SH1_TRAP26_VECOFFSET (58*4) /* 58: " " " " " " " " */
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#define SH1_TRAP27_VECOFFSET (59*4) /* 59: " " " " " " " " */
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#define SH1_TRAP28_VECOFFSET (60*4) /* 60: " " " " " " " " */
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#define SH1_TRAP29_VECOFFSET (61*4) /* 61: " " " " " " " " */
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#define SH1_TRAP30_VECOFFSET (62*4) /* 62: " " " " " " " " */
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#define SH1_TRAP31_VECOFFSET (63*4) /* 63: " " " " " " " " */
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/* Interrupts */
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#define SH1_IRQ_VECOFFSET (64*4) /* 64-71: IRQ0-7 */
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#define SH1_IRQ0_VECOFFSET (64*4) /* 64: IRQ0 */
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#define SH1_IRQ1_VECOFFSET (65*4) /* 65: IRQ1 */
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#define SH1_IRQ2_VECOFFSET (66*4) /* 66: IRQ2 */
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#define SH1_IRQ3_VECOFFSET (67*4) /* 67: IRQ3 */
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#define SH1_IRQ4_VECOFFSET (68*4) /* 68: IRQ4 */
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#define SH1_IRQ5_VECOFFSET (69*4) /* 69: IRQ5 */
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#define SH1_IRQ6_VECOFFSET (70*4) /* 70: IRQ6 */
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#define SH1_IRQ7_VECOFFSET (71*4) /* 71: IRQ7 */
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/* On-chip modules -- The following may be unique to the 7032 */
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#ifdef CONFIG_ARCH_SH7032
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/* DMAC */
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#define SH1_DMAC0_VECOFFSET (72*4) /* 72-73: DMAC0 */
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#define SH1_DEI0_VECOFFSET (72*4) /* 72: DMAC0 DEI0 */
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/* 73: Reserved */
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#define SH1_DMAC1_VECOFFSET (74*4) /* 74-75: DMAC1 */
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#define SH1_DEI1_VECOFFSET (74*4) /* 74: DMAC1 DEI1 */
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/* 75: Reserved */
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#define SH1_DMAC2_VECOFFSET (76*4) /* 76-77: DMAC2 */
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#define SH1_DEI2_VECOFFSET (76*4) /* 76: DMAC2 DEI2 */
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/* 77: Reserved */
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#define SH1_DMAC3_VECOFFSET (78*4) /* 78-79: DMAC3 */
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#define SH1_DEI3_VECOFFSET (78*4) /* 78: DMAC3 DEI3 */
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/* 79: Reserved */
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/* ITU */
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#define SH1_IMIA0_VECOFFSET (80*4) /* 80: ITU0 IMIA0 */
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#define SH1_IMIBO_VECOFFSET (81*4) /* 81: IMIB0 */
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#define SH1_OVI0_VECOFFSET (82*4) /* 82: OVI0 */
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/* 83: Reserved */
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#define SH1_IMIA1_VECOFFSET (84*4) /* 84: ITU1 IMIA1 */
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#define SH1_IMIB1_VECOFFSET (85*4) /* 85: IMIB1 */
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#define SH1_OVI1_VECOFFSET (86*4) /* 86: OVI1 */
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/* 87: Reserved */
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#define SH1_IMIA2_VECOFFSET (88*4) /* 88: ITU2 IMIA2 */
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#define SH1_IMIB2_VECOFFSET (89*4) /* 89: IMIB2 */
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#define SH1_OVI2_VECOFFSET (90*4) /* 90: OVI2 */
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/* 91: Reserved */
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#define SH1_IMIA3_VECOFFSET (92*4) /* 92: ITU3 IMIA3 */
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#define SH1_IMIB3_VECOFFSET (93*4) /* 93: IMIB3 */
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#define SH1_OVI3_VECOFFSET (94*4) /* 94: OVI3 */
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/* 95: Reserved */
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#define SH1_IMIA4_VECOFFSET (96*4) /* 96: ITU4 IMIA4 */
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#define SH1_IMIB4_VECOFFSET (97*4) /* 97: IMIB4 */
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#define SH1_OVI4_VECOFFSET (98*4) /* 98: OVI4 */
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/* 99: Reserved */
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/* SCI */
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#define SH1_ERI0_VECOFFSET (100*4) /* 100: SCI0 ERI0 */
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#define SH1_RXI0_VECOFFSET (101*4) /* 101: RxI0 */
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#define SH1_TXI0_VECOFFSET (102*4) /* 102: TxI0 */
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#define SH1_TEI0_VECOFFSET (103*4) /* 103: TEI0 */
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#define SH1_ERI1_VECOFFSET (104*4) /* 104: SCI1 ERI1 */
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#define SH1_RXI1_VECOFFSET (105*4) /* 105: RxI1 */
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#define SH1_TXI1_VECOFFSET (106*4) /* 106: TxI1 */
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#define SH1_TEI1_VECOFFSET (107*4) /* 107: TEI1 */
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#define SH1_PEI_VECOFFSET (108*4) /* 108: Parity control unit PEI */
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#define SH1_ADITI_VECOFFSET (109*4) /* 109: A/D ITI */
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/* 110-111: Reserved */
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#define SH1_WDTITI_VECOFFSET (112*4) /* 112: WDT ITI */
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#define SH1_CMI_VECOFFSET (113*4) /* 113: REF CMI */
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/* 114-115: Reserved */
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/* 116-255 reserved */
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#endif
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/* IRQ Stack Frame Format. The SH-1 has a push down stack. The PC
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* and SR are pushed by hardware at the time an IRQ is taken.
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*/
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/* Saved to the stacked by up_vector */
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#define REG_R0 (0)
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#define REG_R1 (1)
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#define REG_R2 (2)
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#define REG_R3 (3)
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#define REG_R5 (5)
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#define REG_R6 (6)
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#define REG_R7 (7)
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#define REG_R8 (8)
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#define REG_R9 (9)
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#define REG_R10 (10)
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#define REG_R11 (11)
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#define REG_R12 (12)
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#define REG_R13 (13)
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#define REG_R14 (14)
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|
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#define REG_PR (15)
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#define REG_GBR (16)
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#define REG_MACH (17)
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#define REG_MACL (18)
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/* Saved to the stack by the trampoline logic */
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#define REG_R4 (19)
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#define REG_R15 (20)
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#define REG_SP REG_R15
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/* Pushed by hardware when the exception is taken */
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#define REG_PC (21)
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#define REG_SR (22)
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#define XCPTCONTEXT_REGS (23)
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#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS)
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|
|
/************************************************************************************
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|
* Public Types
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|
************************************************************************************/
|
|
|
|
/************************************************************************************
|
|
* Public Data
|
|
************************************************************************************/
|
|
|
|
#ifndef __ASSEMBLY__
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|
#ifdef __cplusplus
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|
#define EXTERN extern "C"
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|
extern "C" {
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|
#else
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|
#define EXTERN extern
|
|
#endif
|
|
|
|
/************************************************************************************
|
|
* Inline Functions
|
|
************************************************************************************/
|
|
|
|
#ifndef __ASSEMBLY__
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|
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|
/* Get the current value of the SR */
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|
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static inline irqstate_t __getsr(void)
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|
{
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|
irqstate_t flags;
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|
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__asm__ __volatile__ ("stc sr, %0" : "=r" (flags));
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return flags;
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}
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|
|
|
/* Set the new value of the SR */
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|
|
|
static inline void __setsr(irqstate_t sr)
|
|
{
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|
__asm__ __volatile__ ("ldc %0, sr" : : "r" (sr));
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|
}
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|
|
|
/* Return the current interrupt enable state & disable IRQs */
|
|
|
|
static inline irqstate_t irqsave(void)
|
|
{
|
|
irqstate_t flags = __getsr();
|
|
__setsr(flags | 0x000000f0);
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|
return flags;
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|
}
|
|
|
|
/* Disable IRQs */
|
|
|
|
static inline void irqdisable(void)
|
|
{
|
|
uint32 flags = __getsr();
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|
__setsr(flags | 0x000000f0);
|
|
}
|
|
/* Enable IRQs */
|
|
|
|
static inline void irqenable(void)
|
|
{
|
|
uint32 flags = __getsr();
|
|
__setsr(flags & ~0x000000f0);
|
|
}
|
|
|
|
/* Restore saved IRQ state */
|
|
|
|
static inline void irqrestore(irqstate_t flags)
|
|
{
|
|
if ((flags & 0x000000f0) != 0x000000f0)
|
|
{
|
|
irqenable();
|
|
}
|
|
else
|
|
{
|
|
irqdisable();
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/************************************************************************************
|
|
* Public Functions
|
|
************************************************************************************/
|
|
|
|
#undef EXTERN
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
#endif /* __ARCH_SH_INCLUDE_SH1_IRQ_H */
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