152 lines
4.0 KiB
C
152 lines
4.0 KiB
C
/****************************************************************************
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* arch/arm/src/stm32/stm32_comp_v1.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32_STM32_COMP_V1_H
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#define __ARCH_ARM_SRC_STM32_STM32_COMP_V1_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#ifdef CONFIG_STM32_COMP
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/****************************************************************************
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* Pre-processor definitions
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****************************************************************************/
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#define COMP_BLANKING_DEFAULT COMP_BLANKING_DIS /* No blanking */
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#define COMP_POL_DEFAULT COMP_POL_NONINVERT /* Output is not inverted */
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#define COMP_INM_DEFAULT COMP_INMSEL_1P4VREF /* 1/4 of Vrefint as INM */
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#define COMP_OUTSEL_DEFAULT COMP_OUTSEL_NOSEL /* Output not selected */
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#define COMP_LOCK_DEFAULT COMP_LOCK_RW /* Do not lock CSR register */
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#ifndef CONFIG_STM32_STM32F33XX
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#define COMP_MODE_DEFAULT
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#define COMP_HYST_DEFAULT
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#define COMP_WINMODE_DEFAULT
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#endif
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/* Blanking source */
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enum stm32_comp_blanking_e
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{
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COMP_BLANKING_DIS,
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#if defined(CONFIG_STM32_STM32F33XX)
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COMP_BLANKING_T1OC5,
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COMP_BLANKING_T3OC4,
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COMP_BLANKING_T2OC3,
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COMP_BLANKING_T3OC3,
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COMP_BLANKING_T15OC1,
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COMP_BLANKING_T2OC4,
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COMP_BLANKING_T15OC2,
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#endif
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};
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/* Output polarisation */
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enum stm32_comp_pol_e
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{
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COMP_POL_NONINVERT,
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COMP_POL_INVERTED
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};
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/* Inverting input */
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enum stm32_comp_inm_e
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{
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COMP_INMSEL_1P4VREF,
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COMP_INMSEL_1P2VREF,
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COMP_INMSEL_3P4VREF,
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COMP_INMSEL_VREF,
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COMP_INMSEL_DAC1CH1,
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COMP_INMSEL_DAC1CH2,
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COMP_INMSEL_PIN
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};
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/* Output selection */
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enum stm32_comp_outsel_e
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{
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COMP_OUTSEL_NOSEL,
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#if defined(CONFIG_STM32_STM32F33XX)
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COMP_OUTSEL_BRKACTH,
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COMP_OUTSEL_BRK2,
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COMP_OUTSEL_T1OCC, /* COMP2 only */
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COMP_OUTSEL_T3CAP3, /* COMP4 only */
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COMP_OUTSEL_T2CAP2, /* COMP6 only */
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COMP_OUTSEL_T1CAP1, /* COMP2 only */
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COMP_OUTSEL_T2CAP4, /* COMP2 only */
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COMP_OUTSEL_T15CAP2, /* COMP4 only */
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COMP_OUTSEL_T2OCC, /* COMP6 only */
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COMP_OUTSEL_T16OCC, /* COMP2 only */
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COMP_OUTSEL_T3CAP1, /* COMP2 only */
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COMP_OUTSEL_T15OCC, /* COMP4 only */
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COMP_OUTSEL_T16CAP1, /* COMP6 only */
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COMP_OUTSEL_T3OCC, /* COMP2 and COMP4 only */
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#endif
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};
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/* CSR register lock state */
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enum stm32_comp_lock_e
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{
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COMP_LOCK_RW,
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COMP_LOCK_RO
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};
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#ifndef CONFIG_STM32_STM32F33XX
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/* Hysteresis */
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enum stm32_comp_hyst_e
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{
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COMP_HYST_DIS,
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COMP_HYST_LOW,
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COMP_HYST_MEDIUM,
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COMP_HYST_HIGH
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};
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/* Power/Speed Modes */
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enum stm32_comp_mode_e
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{
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COMP_MODE_HIGHSPEED,
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COMP_MODE_MEDIUMSPEED,
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COMP_MODE_LOWPOWER,
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COMP_MODE_ULTRALOWPOWER
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};
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/* Window mode */
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enum stm32_comp_winmode_e
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{
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COMP_WINMODE_DIS,
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COMP_WINMODE_EN
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};
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#endif
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#endif /* CONFIG_STM23_COMP */
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#endif /* __ARCH_ARM_SRC_STM32_STM32_COMP_V1_H */
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