149 lines
5.5 KiB
C
149 lines
5.5 KiB
C
/****************************************************************************
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* arch/arm/include/spinlock.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_SPINLOCK_H
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#define __ARCH_ARM_INCLUDE_SPINLOCK_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif /* __ASSEMBLY__ */
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* Spinlock states */
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#define SP_UNLOCKED 0 /* The Un-locked state */
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#define SP_LOCKED 1 /* The Locked state */
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/* Memory barriers for use with NuttX spinlock logic
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*
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* Data Memory Barrier (DMB) acts as a memory barrier. It ensures that all
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* explicit memory accesses that appear in program order before the DMB
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* instruction are observed before any explicit memory accesses that appear
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* in program order after the DMB instruction. It does not affect the
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* ordering of any other instructions executing on the processor
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*
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* dmb st - Data memory barrier. Wait for stores to complete.
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*
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* Data Synchronization Barrier (DSB) acts as a special kind of memory
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* barrier. No instruction in program order after this instruction executes
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* until this instruction completes. This instruction completes when: (1) All
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* explicit memory accesses before this instruction complete, and (2) all
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* Cache, Branch predictor and TLB maintenance operations before this
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* instruction complete.
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*
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* dsb sy - Data syncrhonization barrier. Assures that the CPU waits until
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* all memory accesses are complete
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*/
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#define SP_DSB() __asm__ __volatile__ ("dsb sy" : : : "memory")
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#define SP_DMB() __asm__ __volatile__ ("dmb st" : : : "memory")
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#ifdef CONFIG_ARM_HAVE_WFE_SEV
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#define SP_WFE() __asm__ __volatile__ ("wfe" : : : "memory")
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#define SP_SEV() __asm__ __volatile__ ("sev" : : : "memory")
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#endif
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/* The Type of a spinlock.
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*
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* ARMv6 architecture introduced the concept of exclusive accesses to memory
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* locations in the form of the Load-Exclusive (LDREX) and Store-Exclusive
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* (STREX) instructions in ARM and Thumb instruction sets. ARMv6K extended
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* this to included byte, halfword, and doubleword variants of LDREX and
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* STREX. ARMv7-M supports byte and halfword, but not the doubleword variant
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* (ARMv6-M does not support exclusive access).
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*
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* ARM architectures prior to ARMv6 supported SWP and SWPB instructions that
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* atomically swap a 32-bit word for byte value between a register and a
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* memory location. From the ARMv6 architecture, ARM deprecates the use
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* of SWP and SWPB.
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*/
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typedef uint8_t spinlock_t;
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: up_testset
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*
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* Description:
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* Perform an atomic test and set operation on the provided spinlock.
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*
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* This function must be provided via the architecture-specific logic.
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*
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* Input Parameters:
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* lock - The address of spinlock object.
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*
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* Returned Value:
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* The spinlock is always locked upon return. The value of previous value
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* of the spinlock variable is returned, either SP_LOCKED if the spinlock
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* as previously locked (meaning that the test-and-set operation failed to
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* obtain the lock) or SP_UNLOCKED if the spinlock was previously unlocked
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* (meaning that we successfully obtained the lock)
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*
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****************************************************************************/
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#if defined(CONFIG_ARCH_HAVE_TESTSET) \
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&& !defined(CONFIG_ARCH_CHIP_LC823450) \
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&& !defined(CONFIG_ARCH_CHIP_CXD56XX) \
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&& !defined(CONFIG_ARCH_CHIP_RP2040)
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static inline_function spinlock_t up_testset(FAR volatile spinlock_t *lock)
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{
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spinlock_t ret = SP_UNLOCKED;
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__asm__ __volatile__
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(
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"1: \n"
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"ldrexb %0, [%2] \n"
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"cmp %0, %1 \n"
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"beq 2f \n"
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"strexb %0, %1, [%2] \n"
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"cmp %0, %1 \n"
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"beq 1b \n"
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"dmb \n"
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"2: \n"
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: "+r" (ret)
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: "r" (SP_LOCKED), "r" (lock)
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: "memory"
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);
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return ret;
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}
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#endif
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/* See prototype in nuttx/include/nuttx/spinlock.h */
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM_INCLUDE_SPINLOCK_H */
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